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SL28610BLI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
SL28610
......................DOC #: SP-AP-0078 (Rev. 1.0) Page 13 of 23
SL28610
......................DOC #: SP-AP-0078 (Rev. 1.0) Page 14 of 23
CPU_STP# Assertion
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable are stopped
within two to six CPU clock periods after sampled by two rising
edges of the internal CPUC clock. The final states of the
stopped CPU signals are CPUT = HIGH and CPUC = LOW.
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal causes all stopped
CPU outputs to resume normal operation in a synchronous
manner. No short or stretched clock pulses are produced when
the clock resumes. The maximum latency from the
deassertion to active outputs is no more than two CPU clock
cycles.
.
.
Note: *Differential clocks output state can be configured through Byte 19 bits 3:.0
CPU_STP#
CPUT
CPUC
Figure 4. CPU_STP# Assertion Waveform
CPU_STP#
CPUT
CPUC
CPUT Internal
Tdrive_CPU_STP#,10 ns>200 mV
CPUC Internal
Figure 5. CPU_STP# Deassertion Waveform
Table 1. Output Driver Status during PCI_STPPCI_STP# and CPU_STP#
CPU_STP# Asserted SMBus Disabled OE# Pins Disabled
Single-ended Clocks Stoppable Running
Driven low Driven low
Non stoppable Running
Differential Clocks Stoppable Clock driven high
Driven Low
Clock driven high*
Clock# driven low Clock# driven low*
Non stoppable Running
SL28610
......................DOC #: SP-AP-0078 (Rev. 1.0) Page 15 of 23
Absolute Maximum Conditions
Parameter Description Condition Min. Max. Unit
3.3V_V
DD
3.3V Supply Voltage Functional –0.5 4.6 V
1.5V_V
DD_CORE
1.5V Supply Voltage Functional –0.5 2.1 V
1.5V_V
DD_IO
DIFF I/O Supply Voltage Functional –0.5 2.1 V
V
IN
Input Voltage Relative to V
SS
–0.5 4.6 V
DC
T
S
Temperature, Storage Non-functional –65 150 °C
T
A
Commercial Temperature,
Operating Ambient
Functional 0 85 °C
Industrial Temperature, Operating
Ambient
-40 +85 °C
T
J
Temperature, Junction Functional – 150 °C
Ø
JC
Dissipation, Junction to Case JEDEC (JESD 51) – 20 °C/W
Ø
JA
Dissipation, Junction to Ambient JEDEC (JESD 51) – 60 °C/W
ESD
HBM
ESD Protection (Human Body
Model)
JEDEC (JESD 22-A114) 2000 – V
UL-94 Flammability Rating UL (CLASS) V–0
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter Description Condition Min. Max. Unit
1.5V_V
DD_CORE
1.5V Operating Voltage 1.5V ± 5% 1.425 1.575 V
1.5V_V
DD_IO
1.5V Differential I/O Supply
Voltage
1.5V ± 5% 1.425 1.575 V
3.3V_V
DD
3.3V Operating Voltage 3.3 ± 5% 3.135 3.465 V
3.3V_V
IH
3.3V Input High Voltage (SE) 3.3V_V
DD
2 3.3V_CORE+ 0.3 V
3.3V_V
IL
3.3V Input Low Voltage (SE) V
SS
– 0.3 0.8 V
V
IHI2C
Input High Voltage SDATA, SCLK 2.2 – V
V
ILI2C
Input Low Voltage SDATA, SCLK – 1.0 V
V
IH_FS
FS_[C,B] Input High Voltage 1.05V_CORE 0.9 1.5V_CORE + 0.3 V
V
IL_FS
FS_[C,B] Input Low Voltage GND-0.3 0.25 V
V
IH
OE# Input High Voltage 1.5V_CORE 1.2 1.5V_CORE + 0.3 V
V
IL
OE# Input Low Voltage GND-0.3 0.3 V
V
IH
PCIe_SEL Input High Voltage 3.3V_CORE 2.0 VDD+0.3 V
V
IL
PCIe_SEL Input Low Voltage GND-0.3 0.8 V
I
IH
Input High Leakage Current Except internal pull-down resistors,
0 < V
IN
< V
DD
–5A
I
IL
Input Low Leakage Current Except internal pull-up resistors, 0
< V
IN
< V
DD
–5 – A
V
OH
3.3V Output High Voltage (SE) I
OH
= –1 mA 2.4 – V
V
OL
3.3V Output Low Voltage (SE) I
OL
= 1 mA – 0.4 V
V
DD IO
Low Voltage IO Supply Voltage 0.72 0.88
I
OZ
High-impedance Output
Current
–10 10 A
C
IN
Input Pin Capacitance 1.5 5 pF
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

SL28610BLI

Mfr. #:
Buy SL28610BLI
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products Atom, Poulsbo, handheld embedded, 1.5V core, PCIe Gen.1
Lifecycle:
New from this manufacturer.
Delivery:
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