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SL28610BLI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
SL28610
........................DOC #: SP-AP-0078 (Rev. 1.0) Page 4 of 23
27:20 Byte Count–8 bits
(Skip this step if I
2
C_EN bit set)
20 Repeat start
28 Acknowledge from slave 27:21 Slave address–7 bits
36:29 Data byte 1–8 bits 28 Read = 1
37 Acknowledge from slave 29 Acknowledge from slave
45:38 Data byte 2–8 bits 37:30 Byte Count from slave–8 bits
46 Acknowledge from slave 38 Acknowledge
.... Data Byte /Slave Acknowledges 46:39 Data byte 1 from slave–8 bits
.... Data Byte N–8 bits 47 Acknowledge
.... Acknowledge from slave 55:48 Data byte 2 from slave–8 bits
.... Stop 56 Acknowledge
.... Data bytes from slave / Acknowledge
.... Data Byte N from slave–8 bits
.... NOT Acknowledge
.... Stop
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol Byte Read Protocol
Bit Description Bit Description
1Start 1Start
8:2 Slave address–7 bits 8:2 Slave address–7 bits
9Write 9Write
10 Acknowledge from slave 10 Acknowledge from slave
18:11 Command Code–8 bits 18:11 Command Code–8 bits
19 Acknowledge from slave 19 Acknowledge from slave
27:20 Data byte–8 bits 20 Repeated start
28 Acknowledge from slave 27:21 Slave address–7 bits
29 Stop 28 Read
29 Acknowledge from slave
37:30 Data from slave–8 bits
38 NOT Acknowledge
39 Stop
Table 3. Block Read and Block Write Protocol (continued)
Block Write Protocol Block Read Protocol
Bit Description Bit Description
SL28610
........................DOC #: SP-AP-0078 (Rev. 1.0) Page 5 of 23
Control Registers
Byte 0: Control Register 0
Bit @Pup Name Description
7 1 PLL1_EN PLL1 Enable
0 = Disabled, 1 = Enabled
6 1 PLL2_EN PLL2 Enable
0 = Disabled, 1 = Enabled
5 1 PLL3_EN PLL3 Enable
0 = Disabled, 1 = Enabled
4 0 RESERVED RESERVED
3 1 CPU_DIV CPU Output Divider Enable
0 = Disabled, 1 = Enabled
2 1 PCIe_DIV PCIe Output Divider Enable
0 = Disabled, 1 = Enabled
1 1 LCD_DIV LCD Output Divider Enable
0 = Disabled, 1 = Enabled
0 1 DOT96_DIV DOT96 Output Divider Enable
0 = Disabled, 1 = Enabled
Byte 1: Control Register 1
Bit @Pup Name Description
7 1 PLL1_Spread _EN PLL1 Spread Enable
0 = Disabled, 1 = Enabled
6 1 PLL3_Spread _EN PLL3 Spread Enable
0 = Disabled, 1 = Enabled
5 0 PLL3_CFB2 PLL3 Spread Spectrum Select
PLL3_CFB[2:0]
000 = -%0.5 (Down Spread) - Default
001 = -%1.0, DS
010 = -%1.5, DS
011 = -% 2.0, DS
100 = %+
0.30 (Center Spread)
101 = %+
0.50, CS
110 = %+
1.00, CS
111 = %+
1.25, CS
4 0 PLL3_CFB1
3 0 PLL3_CFB0
2 0 RESERVED RESERVED
1 0 RESERVED RESERVED
0 0 RESERVED RESERVED
Byte 2: Control Register 2
Bit @Pup Name Description
7 1 CPU0_OE Output enable for CPU0
0 = Output Disabled, 1 = Output Enabled
6 1 CPU1_OE Output enable for CPU1
0 = Output Disabled, 1 = Output Enabled
5 1 CPU2_OE Output enable for CPU2
0 = Output Disabled, 1 = Output Enabled
4 1 PCIe0_OE Output enable for PCIe0
0 = Output Disabled, 1 = Output Enabled
3 1 PCIe1_OE Output enable for PCIe1
0 = Output Disabled, 1 = Output Enabled
SL28610
........................DOC #: SP-AP-0078 (Rev. 1.0) Page 6 of 23
2 1 PCIe2_OE Output enable for SCR2
0 = Output Disabled, 1 = Output Enabled
1 1 DOT96_OE Output enable for DOT96
0 = Output Disabled, 1 = Output Enabled
0 1 LCD_OE Output enable for LCD
0 = Output Disabled, 1 = Output Enabled
Byte 2: Control Register 2 (continued)
Bit @Pup Name Description
Byte 3: Control Register 3
Bit @Pup Name Description
7 1 RESERVED RESERVED
6 1 RESERVED RESERVED
5 1 REF_OE Output enable for REF
0 = Output Disabled, 1 = Output Enabled
4 1 REF_Bit1 REF Slew Rate Control Bit2
(see Byte 16 Bit [7:6] for Slew Rate REF_Bit0 & REF_Bit2)
0 = 1 load, 1 = 2 loads
3 0 RESERVED RESERVED
2 0 CPU0_STP# CPU0 CPU_STP# Control
0 = Free Running, 1 = Stopped with CPU_STP#
1 0 CPU1_STP# CPU1 CPU_STP# Control
0 = Free Running, 1 = Stopped with CPU_STP#
0 0 CPU2_STP# CPU2 CPU_STP# Control
0 = Free Running, 1 = Stopped with CPU_STP#
Byte 4: Control Register 4
Bit @Pup Name Description
7 HW PLL1 M DIV 7 This is a read only register of the multiplier used for PLL1 M Divider
HW= Read Only
6 HW PLL1 M DIV 6
5 HW PLL1 M DIV 5
4 HW PLL1 M DIV 4
3 HW PLL1 M DIV 3
2 HW PLL1 M DIV 2
1 HW PLL1 M DIV 1
0 HW PLL1 M DIV 0
Byte 5: Control Register 5
Bit @Pup Name Description
7 HW PLL1 N DIV 7 This is a read only register of the multiplier used for PLL1 N Divider
HW= Read Only
6 HW PLL1 N DIV 6
5 HW PLL1 N DIV 5
4 HW PLL1 N DIV 4
3 HW PLL1 N DIV 3
2 HW PLL1 N DIV 2
1 HW PLL1 N DIV 1
0 HW PLL1 N DIV 0
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SL28610BLI

Mfr. #:
Buy SL28610BLI
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products Atom, Poulsbo, handheld embedded, 1.5V core, PCIe Gen.1
Lifecycle:
New from this manufacturer.
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