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5V41068APGGI8

P1-P3P4-P6P7-P9P10-P12P13-P13
DATASHEET
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER IDT5V41068A
IDT®
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 1
IDT5V41068A REV F 040616
Description
The IDT5V41068A is a 2:1 differential clock mux for PCI
Express applications. It has very low additive jitter making it
suitable for use in PCIe Gen2 and Gen3 systems. The
IDT5V41068A selects between 1 of 2 differential HCSL
inputs to drive a single differential HCSL output pair. The
output can also be terminated to LVDS.
Recommended Applications
• Clock muxing in PCIe Gen2 and Gen3 applications
Output Features
• 1 – 0.7V current mode differential HCSL output pair
Features/Benefits
• Low additive jitter; suitable for use in PCIe Gen2 and
Gen3 systems
• 16-pin TSSOP package; small board footprint
• Outputs can be terminated to LVDS; can drive a wider
variety of devices
• OE control pin; greater system power management
• Industrial temperature range available; supports
demanding embedded applications
Key Specifications
• Additive cycle-to-cycle jitter <5 ps
• Additive phase jitter (PCIe Gen3) <0.2ps
• Operating frequency up to 200MHz
Block Diagram
VDD
Rr (IREF)
CLK
CLK
SEL GND
IN1
IN1
IN2
IN2
MUX
2 to 1
OE
3
3
PD
IDT5V41068A
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER
IDT®
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 2
IDT5V41068A REV F 040616
Pin Assignment Select Table
Pin Descriptions
VDDIN 1 16 ^SEL
DIF_IN1 2 15 DIF_0
DIF_IN1# 3 14 DIF_0#
^PD# 4 13 GND
DIF_IN2 5 12 GND
DIF_IN2# 6 11 VDD
^OE 7 10 VDD
GND
89
IREF
16-pin TSSOP
5V41068
Note :
Pins preceeded by '*^ have internal
120K ohm pull up resistors
SEL Outputs
0DIF_IN2
1DIF_IN1
PIN # PIN NAME PIN TYPE DESCRIPTION
1 VDDIN PWR Power
p
in for the In
p
uts, nominal 3.3V
2 DIF_IN1 IN 0.7 V Differential TRUE in
p
ut
3 DIF_IN1# IN 0.7 V Differential Com
p
lementar
y
In
p
ut
4^PD# IN
Asynchronous active low input pin used to power down the device. The internal
clocks are disabled and the VCO and the crystal osc. (if any) are stopped.
5 DIF_IN2 IN 0.7 V Differential TRUE input
6 DIF_IN2# IN 0.7 V Differential Com
p
lementar
y
In
p
ut
7^OE IN
Active high input for enabling outputs. This pin has an internal pull up resistor.
0 = disable outputs, 1= enable outputs
8 GND PWR Ground pin.
9IREF OUT
This pin establishes the reference for the differential current-mode output pairs. It
requires a fixed precision resistor to ground. 475ohm is the standard value for
100ohm differential impedance. Other impedances require different values. See
data sheet.
10 VDD PWR Power su
pp
l
y
, nominal 3.3V
11 VDD PWR Power su
pp
l
y
, nominal 3.3V
12 GND PWR Ground pin.
13 GND PWR Ground pin.
14 DIF_0# OUT 0.7V differential Complementary clock output
15 DIF_0 OUT 0.7V differential true clock out
ut
16 ^SEL IN Selects between one of two inputs. This pin has internal pull up resistor.
IDT5V41068A
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER
IDT®
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 3
IDT5V41068A REV F 040616
Application Information
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
IDT5V41068A must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the IDT5V41068A.
This includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the device.
External Components
A minimum number of external components are required for
proper operation. Decoupling capacitors of 0.01F should
be connected between VDD and GND pairs (2,9 and 15,16)
as close to the device as possible.
Current Reference Source R
r
(Iref)
If board target trace impedance (Z) is 50, then Rr = 475
(1%), providing IREF of 2.32 mA, output current (I
OH
) is
equal to 6*IREF.
Load Resistors R
L
Since the clock outputs are open source outputs, 50 ohm
external resistors to ground are to be connected at each
clock output.
Output Termination
The PCI-Express differential clock outputs of the
IDT5V41068A are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown in
detail in the Layout Guidelines section.
The IDT5V41068A can also be terminated to LVDS
compatible voltage levels. See the Layout Guidelines
section.
P1-P3P4-P6P7-P9P10-P12P13-P13

5V41068APGGI8

Mfr. #:
Buy 5V41068APGGI8
Manufacturer:
IDT
Description:
Clock Drivers & Distribution PCIe Gen2/3 2:1 DIFF CLOCK MUX
Lifecycle:
New from this manufacturer.
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