IDT5V41068A
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER
IDT®
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 7
IDT5V41068A REV F 040616
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT5V41068A. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only
over the recommended operating temperature range.
Electrical Characteristics–Input/Supply/Common Parameters
PARAMETER SYMBOL CONDITIONS
MIN TYP MAX
UNITS NOTES
3.3V Logic Supply Voltage VDD 4.6 V 1,2
Input Low Voltage V
IL
GND-0.5 V
1
Input High Voltage V
IH
V
DD
+0.5V V 1
Storage Temperature Ts -65 150
°
C1
Junction Temperature Tj 125 °C
1
Input ESD protection
ESD prot Human Body Model 2000 V
1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor guaranteed.
TA = T
COM
or T
I ND;
Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading C onditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
T
COM
Commmercial range 0 70 °C 1
T
IND
Industrial range -40 85 °C 1
Input High Voltage
V
IH
Single-ended inputs, excep
t
SMBus, low threshold
and tri-level in
p
uts, if
p
re se nt
2.2
V
DD
+ 0.3
V1
Input Low Voltage
V
IL
Single-ended inputs, excep
t
SMBus, low threshold
and tri-level in
p
uts, if
p
re se nt
GND
- 0.3
0.8 V 1
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= VDD -5 5 uA 1
I
IN P
Sin gle -ended inp uts
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
-200 200 uA 1
Input Frequency F
ibyp
V
DD
= 3.3 V, Bypass mode 200 MHz 2
Pin Inductance
L
p
in
7nH1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
IN DIF_IN
Differential clock inputs 1.5 2.7 pF 1,4
C
OUT
Output pin capacitance 6 pF 1
OE Latency
t
LAT OE#
DIF start after OE# assertion
DIF stop after OE# deassertion
13clocks1,3,5
PD# Latency
t
STABPD#
DIF driven to 200mV after PDE# assertion 300 usec 1,3,5
Tfall t
F
Fall time of control inputs 5 ns 1,2
Trise t
R
Rise time of control inputs 5 ns 1,2
1
Guaranteed by design and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swing.
5
The differential input clock must be running for the OE pin to work
Ambient Operating
Temperature
Input Current
3
Time from deassertion until outputs are >200 mV
4
INA/B inputs
Capacitance
IDT5V41068A
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER
IDT®
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 8
IDT5V41068A REV F 040616
Electrical Characteristics–Clock Input Parameters
Electrical Characteristics–DIF 0.7V Current Mode Differential Outputs
Electrical Characteristics–Current Consumption
TA = T
COM
or T
IND;
Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS N OTES
Input High Voltage - DIF_IN
V
IHDIF
Differential inputs
(
sin
g
le-ended measurement
)
600 800 1150 mV 1
Input Low Voltage - DIF_IN
V
IL DIF
Differential inputs
(
sin
g
le-ended measurement
)
V
SS
- 300
0300mV1
Input Common Mode Voltage
- DIF_IN
V
COM
Common Mode Input Voltage 300 1000 mV 1
Input Amplitude - DIF_IN V
SWING
Peak to Peak value 300 1450 mV 1
Input Slew Rate - DIF_IN dv/dt Measured differentially 1 8 V/ns 1,2
Input Leakage Current
I
IN
V
IN
= V
DD ,
V
IN
=
GND
-5 5 uA 1
Input Duty Cycle d
tin
Measurement from differential wavefrom 45 55 % 1
Input Jitter - Cycle to Cycle J
DIF In
Differential Measurement 0 125 ps 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured through +/-75mV window centered around differential zero.
TA = T
COM
or T
IND;
Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Slew rate Trf Scope averaging on 1.5 2.9 4
V/ns
1, 2, 3
Slew rate matching
Trf Slew rate matching, Scope averaging on 14 20
%
1, 2, 4
Voltage High VHigh 660 761 850 1
Voltage Low VLow -150 0.6 150 1
Max Voltage Vmax 860 1150 1
Min Voltage Vmin -300 -78 1
Vswing Vswing Scope averaging off 300 1531 mV 1, 2
Crossing Voltage (abs) Vcross_abs Scope averaging off 250 354 550 mV 1, 5
Crossing Voltage (var)
-Vcross Scope averaging off -29 140 mV 1, 6
2
Measured from differential waveform
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross
absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.
mV
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
Measurement on single ended signal using
absolute value. (Scope averaging off)
mV
1
Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xR
R
). For R
R
= 475
(1%), I
REF
= 2.32mA.
I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
(100
differential impedance).
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate of Clock / falling edge rate of Clock#. It is measured in a +/-75mV window centered on the average
cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope
uses for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
TA = T
COM
or T
IND;
Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Operating Supply Current I
DD3.3OP
All outputs active @100MHz, C
L
= 2 pF; 40 mA 1
Power Down Current
I
DD3 .3PD
PD# pin low, input clock stopped 5 mA
1
1
Guaranteed by design and characterization, not 100% test ed in production.
IDT5V41068A
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER
IDT®
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 9
IDT5V41068A REV F 040616
Electrical Characteristics–Output Duty Cycle, Jitter, and Skew Characteristics
Electrical Characteristics–PCIe Phase Jitter Parameter
TA = T
COM
or T
IND;
Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Duty Cycle t
D
C
When driven by 932SQ420 or equivalent 45 49 55 % 1
Duty Cycle Distortion t
DCD
Measured differentially, @100MHz -2 1 2 % 1,4
Skew, Input to Output t
p
dBYP
V
T
= 50% 2500 3299 4500 ps 1
Additive Jitter t
jcyc-cyc
Cycle to cycle Additive Jitter 1 5 ps 1,3
1
Guaranteed by design and characterization, not 100% tested in production.
2
I
REF
= V
DD
/(3xR
R
). For R
R
= 475
(1%), I
REF
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
.
3
Measured from differential waveform
4
Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
TA = T
COM
or T
IND;
Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
t
jphPCIeG1
PCIe Gen 1 1 2 ps (p-p) 1,2,3,6
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.1 0.2
ps
(rms)
1,2,5,6
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
0.1 0.2
ps
(rms)
1,2,5,6
t
jphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
0.1
0.2
ps
(rms)
1,2,4,5,
6
1
Applies to all outputs.
5
For RMS fi
g
ures, additive jitter is calculated by solvin
g
the followin
g
equation: Additive jitter = SQRT[(total jittter)^2 - (input jitter)^2]
6
Applies to 100MHz spread off and 0.5% down spread sources only.
3
Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4
Subject to final radification by PCI SIG.
2
See http://www.pcisig.com for complete specs
t
jphPCIeG2
Additive Phase Jitter
33
HCSL Output
33
5050
HCSL Differential Output Test Load
2pF 2pF
Zo=100ohm differential

5V41068APGGI8

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution PCIe Gen2/3 2:1 DIFF CLOCK MUX
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet