5V41068APGGI8 Datasheet 5V41068APGGI8, 5V41068APGG8, 5V41068APGG | P4-P6

IDT5V41068A

2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER

IDT®

2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 4

IDT5V41068A REV F 040616

Output Structures

General PCB Layout Recommendations

For optimum device performance and lowest output phase

noise, the following guidelines should be observed.

1. Each 0.01µF decoupling capacitor should be mounted on

the component side of the board as close to the VDD pin as

possible.

2. No vias should be used between decoupling capacitor

and VDD pin.

3. The PCB trace to VDD pin should be kept as short as

possible, as should the PCB trace to the ground via.

Distance of the ferrite bead and bulk decoupling from the

device is less critical.

4. An optimum layout is one with all components on the

same side of the board, minimizing vias through other signal

layers (any ferrite beads and bulk decoupling capacitors can

be mounted on the back). Other signal traces should be

routed away from the IDT5V41068A.This includes signal

traces just underneath the device, or on layers adjacent to

the ground plane layer used by the device.

475

6*IREF

=2.3 mA

IREF

See Layout Guidelines

Sections - Pages 5, 6



IDT5V41068A

2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER

IDT®

2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 5

IDT5V41068A REV F 040616

Layout Guidelines

Common R ecommendations for Differential Routing Dimension or Value Unit Figure

L1 length, route as non-coupled 50ohm trace 0.5 max inch 1

L2 length, route as non-coupled 50ohm trace 0.2 max inch 1

L3 length, route as non-coupled 50ohm trace 0.2 max inch 1

Rs 33 ohm 1

Rt 49.9 ohm 1

Down Device Differential Routing

L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1

L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1

Differential Routing to PCI Express Connector

L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2

L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2

PCIe (SRC) Reference Clock

HCSL Output Buffer

L1'

L2'

L4'

L3L3'

Rt Rt

PCI Express

Down Device

REF_CLK Input

Figure 1: Down Device Routing

HCSL Output Buffer

L1'

L2'

L4'

L3L3'

Rt Rt

PCI Express

Add-in Board

REF_CLK Input

Figure 2: PCI Express Connector Routing

IDT5V41068A

2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER

IDT®

2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 6

IDT5V41068A REV F 040616

Vdiff Vp-p Vcm R1 R2 R3 R4 Note

0.45v 0.22v 1.08 33 150 100 100

0.58 0.28 0.6 33 78.7 137 100

0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible

0.60 0.3 1.2 33 174 140 100 Standard LVDS

R1a = R1b = R1

R2a = R2b = R2

Alternative Termination for LVDS and other Common Differential Signals (figure 3)

HCSL Output Buffer

L1'

R1b

L2'

R1a

L4'

R2a R2b

Down Device

REF_CLK Input

Figure 3

L3'

R3 R4

Component Value Note

R5a, R5b 8.2K 5%

R6a, R6b 1K 5%

Cc 0.1 µF

Vcm 0.350 volts

Cable Connected AC Coupled Application (figure 4)

PCIe Device

REF_CLK Input

Figure 4

R5a

L4'

3.3 Volts

R5b

R6a R6b

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

5V41068APGGI8

Mfr. #:

Buy 5V41068APGGI8

Manufacturer:

IDT

Description:

Clock Drivers & Distribution PCIe Gen2/3 2:1 DIFF CLOCK MUX

Lifecycle:

New from this manufacturer.

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5V41068APGGI8

5V41068APGGI8

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