ISL6627
10
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FN6992.1
January 24, 2014
For additional products, see www.intersil.com/en/products.html
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE REVISION CHANGE
January 24, 2014 FN6992.1 On page 3 - added pin 10 to the description:
PHASE - Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
On page 10 - Updated "Products" verbiage to "About Intersil" verbiage
On page 11 - Updated POD L10.3x3 from rev 6 to rev 9.
Updates since rev 6:
Removed package outline and included center to center distance between lands on recommended land pattern.
Removed Note 4 "Dimension b applies to the metallized terminal and is measured between 0.18mm and 0.30mm
from the terminal tip." since it is not applicable to this package. Renumbered notes accordingly.
Corrected L-shaped leads in Bottom view and land pattern so that they align with the rest of the leads (L shaped
leads were shorter).
Added missing dimension 0.415 in Typical Recommended land pattern.
September 22, 2011 FN6992.0 Initial release.
ISL6627
11
FN6992.1
January 24, 2014
Package Outline Drawing
L10.3x3
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 9, 10/13
located within the zone indicated. The pin #1 identifier may be
Unless otherwise specified, tolerance : Decimal ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optional, but must be
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
5.
either a mold or mark feature.
3.
4.
2.
Dimensions are in millimeters.1.
NOTES:
BOTTOM VIEW
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
(4X) 0.10
INDEX AREA
PIN 1
PIN #1 INDEX AREA
C
SEATING PLANE
BASE PLANE
0.08
SEE DETAIL "X"
C
C
4
5
5
A
B
0.10
C
1
1.00
0.20
8x 0.50
2.00
3.00
(10x 0.23)
(8x 0.50)
2.00
1.60
(10 x 0.55)
3.00
0.05
0.20 REF
10 x 0.23
10x 0.35
1.60
MAX
(4X) 0.10
AB
C
M
0.415
0.23
0.35
0.200
2
2.85 TYP
0.415

ISL6627IRZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Gate Drivers SYNCH BUCK MSFT 5V DRVR VR12 3X3
Lifecycle:
New from this manufacturer.
Delivery:
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