RT8204LGQW Datasheet RT8204LGQW | P13-P15

RT8204L

DS8204L-04 April 2011 www.richtek.com

LIMIT SENSE

ILIM

I x R

R =

20μA

Carefully observe the PC board layout guidelines to ensure

that noise and DC errors do not corrupt the current sense

signal seen by OC and PGND. Mount the IC close to the

low-side MOSFET and sense resistor with short, direct

traces, making a Kelvin sense connection to the sense

resistor.

MOSFET Gate Driver (UGATE, LGATE)

The high side driver is designed to drive high current, low

DS(ON)

N-MOSFET(s). When configured as a floating driver,

5V bias voltage is delivered from VDDP supply. The average

drive current is proportional to the gate charge at V

5V times the switching frequency. The instantaneous drive

current is supplied by the flying capacitor between BOOT

and PHASE pins.

A dead time to prevent shoot through is internally

generated between high side MOSFET off to low side

MOSFET on, and low side MOSFET off to high side

MOSFET on.

The low side driver is designed to drive high current, low

DS(ON)

N-MOSFET(s). The internal pull down transistor

that drives LGATE low is robust, with a 0.6Ω typical on

resistance. A 5V bias voltage is delivered form VDDP

supply. The instantaneous drive current is supplied by the

flying capacitor between VDDP and PGND.

For high current applications, some combinations of high

and low side MOSFETs might be encountered that will

cause excessive gate-drain coupling, which can lead to

efficiency-killing, EMI producing shoot through currents.

This is often remedied by adding a resistor in series with

BOOT, which increases the turn-on time of the high side

MOSFET without degrading the turn-off time (Figure 4).

BOOT

UGATE

PHASE

+5V

Figure 4. Reducing the UGATE Rise Time

Power Good Output (PGOOD)

The power good output is an open-drain output and requires

a pull up resistor. When the output voltage is 15% above

or 10% below its set voltage, PGOOD gets pulled low. It

is held low until the output voltage returns to within these

tolerances once more. In soft start, PGOOD is actively

held low and is allowed to transition high until soft start is

over and the output reaches 93% of its set voltage. There

is a 2.5μs delay built into PGOOD circuitry to prevent

false transition.

POR, UVLO and Soft-Start

Power on reset (POR) occurs when V

rises above to

approximately 4.1V. The RT8204L will reset the fault latch

and prepare the PWM for operation. At below 3.7V (min),

the VDD under voltage lockout (UVLO) circuitry inhibits

switching by keeping UGATE and LGATE low.

A built in soft-start is used to prevent surge current from

power supply input after EN/DEM is enabled. It clamps

the ramping of internal reference voltage which is compared

with the FB signal. The typical soft-start duration is 1.5ms.

Output Over Voltage Protection (OVP)

The output voltage can be continuously monitored for over

voltage protection. When the output voltage exceeds 15%

of its set voltage threshold, over voltage protection is

triggered and the low side MOSFET is latched on. This

activates the low side MOSFET to discharge the output

capacitor.

The RT8204L is latched once OVP is triggered and can

only be released by VDD or EN/DEM power-on reset. There

is a 20μs delay built into the over voltage protection circuit

to prevent false transitions.

MOSFET will not be turned on until the voltage drop across

the sense element (resistor or MOSFET) falls below the

voltage across the R

ILIM

resistor.

Choose a current limit resistor by the following equation :

RT8204L

DS8204L-04 April 2011www.richtek.com

Output Under Voltage Protection (UVP)

The output voltage can be continuously monitored for under

voltage protection. When the output voltage is less than

70% of its set voltage threshold, under voltage protection

is triggered and then both UGATE and LGATE gate drivers

are forced low. In order to remove the residual charge on

the output capacitor during the under voltage period, if

PHASE is greater than 1V, the LGATE is forced high until

PHASE is lower than 1V. There is 2.5μs delay built into

the under voltage protection circuit to prevent false

transitions. During soft-start, the UVP will be blanked

around 4.5ms.

Output Voltage Setting (FB)

The output voltage can be adjusted from 0.75V to 3.3V by

setting the feedback resistors R7 and R8 (Figure 5).

Choose R8 to be approximately 10kΩ, and solve for R7

using the equation :

OUT FB

V = V x 1 +

⎛⎞

⎜⎟

⎝⎠

where V

is 0.75V.

Figure 5. Setting The Output Voltage

Output Inductor Selection

The switching frequency (on-time) and operating point

(% ripple or LIR) determine the inductor value as follows :

ON IN OUT

LOAD(MAX)

t x (V V )

L =

LIR x I

−

Find a low pass inductor having the lowest possible DC

resistance that fits in the allowed dimensions. Ferrite cores

are often the best choice, although powdered iron is

inexpensive and can work well at 200kHz. The core must

be large enough not to saturate at the peak inductor current

PEAK

) :

PEAK LOAD(MAX) LOAD(MAX)

LIR

I = I + x I

⎛⎞

⎜⎟

⎝⎠

Output Capacitor Selection

The output filter capacitor must have ESR low enough to

meet output ripple and load transient requirement, yet have

high enough ESR to satisfy stability requirements. Also,

the capacitance value must be high enough to absorb the

inductor energy going from a full load to no load condition

without tripping the OVP circuit.

For CPU core voltage converters and other applications

where the output is subject to violent load transient, the

output capacitor's size depends on how much ESR is

needed to prevent the output from dipping too low under a

load transient. Ignoring the sag due to finite capacitance :

P P

LOAD(MAX)

ESR

−

≤

In non-CPU applications, the output capacitor's size

depends on how much ESR is needed to maintain at an

acceptable level of output voltage ripple :

P P

LOAD(MAX)

ESR

LIR x I

−

≤

Organic semiconductor capacitor(s) or special polymer

capacitor(s) are recommended.

Output Capacitor Stability

Stability is determined by the value of the ESR zero relative

to the switching frequency. The point of instability is given

by the following equation :

OUT

f = <

2 x x ESR x C 4

Do not put high value ceramic capacitors directly across

the outputs without taking precautions to ensure stability.

Large ceramic capacitors can have a high-ESR zero

frequency and cause erratic and unstable operation.

However, it is easy to add sufficient series resistance by

placing the capacitors a couple of inches downstream from

the inductor and connecting VOUT or the FB divider close

to the inductor.

PHASE

LGATE

OUT

UGATE

VOUT

GND

RT8204L

DS8204L-04 April 2011 www.richtek.com

There are two related but distinct ways, double pulsing

and feedback loop instability to identify the unstable

operation.

Double pulsing occurs due to noise on the output or

because the ESR is too low such that there is not enough

voltage ramp in the output voltage signal. This“fools” the

error comparator into triggering a new cycle immediately

after the 400ns minimum off-time period has expired.

Double pulsing is more annoying than harmful, resulting

in nothing worse than increased output ripple. However, it

may indicate the possible presence of loop instability,

which is caused by insufficient ESR.

Loop instability can result in oscillation at the output after

line or load perturbations and trip the over voltage

protection latch or cause the output voltage to fall below

the tolerance limit.

The easiest method for stability checking is to apply a

very zero-to-max load transient and carefully observe the

output-voltage-ripple envelope for overshoot and ringing. It

helps to simultaneously monitor the inductor current with

an AC probe. Do not allow more than one ringing cycle

after the initial step response under shoot or over shoot.

LDO Normal Operation

The RT8204L LDO controls an N-MOSFET to produce a

tightly regulated output voltage from higher supply voltage.

It takes 5V power supply for controller and draws maximally

400μA while operating.

The feedback voltage is regulated to compare with the

internal 0.75V reference voltage. To set the output voltage,

feedback the conjunction of a resistive voltage divider from

output node to ground for the LFB pin.

Depending upon the input voltage used for the device, the

LDRV pin can pull up near to VDD. Thus, the device can

be used to regulate a large range of output voltage by

careful selection of the external MOSFETs.

The RT8204L LDO includes an active high enable control

(LEN pin) used to turn on RT8204L LDO. If this pin is

pulled low, the LDRV pin is pulled low, turning off the

N-MOSFET. If this pin is pulled higher than 1.2V, the LDRV

pin is enabled.

The RT8204L LDO contains a power good output pin

(LPGOOD pin), which is an open drain output that pulled

low if the output is below the power good threshold

(typically 90% of the programmed output voltage, or 93%

at start up). The power good detection is active if the

RT8204L LDO is enabled.

Also included is an under voltage protection circuit that

monitors the output voltage. If the output voltage drops

below 50% (typical) of nominal, as would occur during

over current or short condition, the RT8204L LDO will pull

the LDRV pin low and latch off. The RT8204L LDO is

latched once UVP is triggered and can only be relieved

by VDD or LEN power on reset.

LDO Driver and Stability Design

The drive output (LDRV pin) is sink/source capable. The

sink current is typically 2mA, while the source current is

typically 2mA in normal operation.

The drive output is also used for stabilizing the loop of the

system using different types of output capacitors. The

components listed in the table below are used.

Table 1. LDO Configuration and Compensation

LDO Configuration Compensator

Input

Voltage

Output

Voltage

C9 C10 R9

1.25V 1.05V 33nF 39pF 82Ω

1.5V 1.05V 33nF 47pF 43Ω

1.5V 1.25V 33nF 47pF 30Ω

1.8V 1.5V 33nF 39pF 100Ω

Note : test condition is output capacitor 220μF (ESR : 9 to

25mΩ) or 100μF (ESR : 9 to 15mΩ) +MLCC 10μF output

current is from 0.1A to 5A

LDO Output Voltage Protection(UVP)

The RT8204L LDO has output under voltage protection

that monitors at the output to check if RT8204L :

(a) LDO output voltage is less than 50% (typical) of its

nominal value and

(b) V

LDRV

is within 900mV (typical) of its maximum.

This provides inherent immunity to under voltage shut down

at start up since V

LDRV

has a slow rate of rising at this

moment. If both of these criteria are met, the output is

shut down by means of pulling V

LDRV

to ground

immediately.

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