RT8204L
17
DS8204L-04 April 2011 www.richtek.com
LDO MOSFET Selection
Low threshold N-MOSFETs are required. For the device
to work under all operating conditions, a maximum R
DS(ON)
must be met to ensure that the output will not go into
dropout :
IN(MIN) OUT(MAX)
DS(ON)(MAX)
OUT(PEAK)
VV
R = ( )
I
−
Ω
Note that R
DS(ON)
must be met for operating temperature
range at the minimum V
GS
condition.
Power consumptions of the N-MOSFETs should be taken
into consideration for the selection of various package
types.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
P
D(MAX)
= (T
J(MAX)
− T
A
) /θ
JA
where T
J(MAX)
is the maximum junction temperature, T
A
is
the ambient temperature, and θ
JA
is the junction to ambient
thermal resistance.
For recommended operating condition specifications of
the RT8204L, the maximum junction temperature is 125°C
and T
A
is the ambient temperature. The junction to ambient
thermal resistance, θ
JA
, is layout dependent. For WQFN-
16L 3x3 packages, the thermal resistance, θ
JA
, is 68°C/
W on a standard JEDEC 51-7 four-layer thermal test board.
The maximum power dissipation at T
A
= 25°C can be
calculated by the following formula :
P
D(MAX)
= (125°C − 25°C ) / (68°C/W) = 1.471W for WQFN-
16L 3x3 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T
J(MAX)
and thermal
resistance, θ
JA
. For the RT8204L package, the derating
curve in Figure 8 allows the designer to see the effect of
rising ambient temperature on the maximum power
dissipation.
Layout Consideration
Layout is very important in high frequency switching
converter design. If designed improperly, the PCB could
radiate excessive noise and contribute to converter
instability. Certain points must be considered before
starting a layout for the RT8204L.
` Connect RC low-pass filter from VDDP to VDD, 1μF and
20Ω are recommended. Place the filter capacitor close
to the IC.
` Keep current limit setting network as close as possible
to the IC. Routing of the network should avoid coupling
to high-voltage switching node.
` Connections from the drivers to the respective gate of
the high side or low side MOSFET should be as short
as possible to reduce stray inductance.
` All sensitive analog traces and components such as
VOUT, FB, GND, EN/DEM, PGOOD, OC, VDD, and
TON should be placed away from high voltage switching
nodes such as PHASE, LGATE, UGATE, or BOOT
nodes to avoid coupling. Use internal layer(s) as ground
plane(s) and shield the feedback trace from power traces
and components.
` Current sense connections must always be made using
Kelvin connections to ensure an accurate signal, with
the current limit resistor located at the device.
` Power sections should connect directly to ground
plane(s) using multiple vias as required for current
handling (including the chip power ground connections).
Power components should be placed to minimize loops
and reduce losses.
Figure 8. Derating Curve for the RT8204L Package
0.00
0.20
0.40
0.60
0.80
1.00
1.20
1.40
1.60
0 25 50 75 100 125
Ambient Temperature (°C)
Maximum Power Dissipation (W) 1
Four-Layer PCB
