MC100ES6254ACR2

DATASHEET
2.5/3.3V Differential LVPECL 2x2 Clock
Switch and Fanout Buffer
MC100ES6254
MC100ES6254 REV. 7 JANUARY 7, 2013 1 ©2013 Integrated Device Technology, Inc.
The Freescale MC100ES6254 is a bipolar monolithic differential 2x2 clock
switch and fanout buffer. Designed for most demanding clock distribution
systems, the MC100ES6254 supports various applications that require a large
number of outputs to drive precisely aligned clock signals. The device is capable
of driving and switching differential LVPECL signals. Using SiGe technology and
a fully differential architecture, the device offers superior digital signal
characteristics and very low clock skew error. Target applications for this clock
driver are high performance clock/data switching, clock distribution or data
loopback in computing, networking and telecommunication systems.
Features
Fully differential architecture from input to all outputs
SiGe technology supports near-zero output skew
Supports DC to 3GHz operation
(1)
of clock or data signals
LVPECL compatible differential clock inputs and outputs
LVCMOS compatible control inputs
Single 3.3 V or 2.5 V supply
50 ps maximum device skew
(1)
Synchronous output enable eliminating output runt pulse generation and
metastability
Standard 32 lead LQFP package
Industrial temperature range
32-lead Pb-free package
Functional Description
MC100ES6254 is designed for very skew critical differential clock distribution
systems and supports clock frequencies from DC up to 3.0GHz. Typical
applications for the MC100ES6254 are primary clock distribution, switching and
loopback systems of high-performance computer, networking and
telecommunication systems, as well as on-board clocking of OC-3, OC-12 and
OC-48 speed communication systems. Primary purpose of the MC100ES6254 is
high-speed clock switching applications. In addition, the MC100ES6254 can be
configured as single 1:6 or dual 1:3 LVPECL fanout buffer for clock signals, or as
loopback device in high-speed data applications.
The MC100ES6254 can be operated from a 3.3 V or 2.5 V positive supply
without the requirement of a negative supply line.
1. The device is functional up to 3GHz and characterized up to 2.7GHz.
ORDERING INFORMATION
Device Package
MC100ES6254AC LQFP-32 (Pb-Free)
MC100ES6254ACR2 LQFP-32 (Pb-Free)
2.5/3.3 V DIFFERENTIAL
LVPECL 2x2
CLOCK SWITCH
AND FANOUT BUFFER
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-04
Product Discontinuance Notice – Last Time Buy Expires on (12/7/2013)
MC100ES6254 REV. 7 JANUARY 7, 2013 2 ©2013 Integrated Device Technology, Inc.
MC100ES6254 Data Sheet 2.5/3.3V DIFFERENTIAL LVPECL 2X2 CLOCK SWITCH AND FANOUT BUFFER
Figure 2. 32-Lead Package Pinout (Top View)
Figure 1. MC100ES6254 Logic Diagram
OEA
SEL0
QA0
QA0
QA1
QA2
QA2
QA1
OEB
QB0
QB0
QB1
QB2
QB2
QB1
CLK0
CLK0
SEL1
V
CC
Bank A
Bank B
SYNC
CLK1
CLK1
V
CC
0
1
0
1
QA2
V
CC
QA1
QA0
QB2
V
CC
QB1
V
CC
V
CC
GND
CLK0
SEL0
GND
V
CC
V
CC
GND
SEL1
CLK1
GND
V
CC
25
26
27
28
29
30
31
32
15
14
13
12
11
10
9
12345678
24 23 22 21 20 19 18 17
16
MC100ES6254
V
CC
QB0
QA2
QA1
QA0
OEA
CLK0
QB2
QB1
QB0
CLK1
OEB
MC100ES6254 REV. 7 JANUARY 7, 2013 3 ©2013 Integrated Device Technology, Inc.
MC100ES6254 Data Sheet 2.5/3.3V DIFFERENTIAL LVPECL 2X2 CLOCK SWITCH AND FANOUT BUFFER
Table 1. Pin Configuration
Pin I/O Type Function
CLK0, CLK0 Input LVPECL Differential reference clock signal input 0
CLK1, CLK1
Input LVPECL Differential reference clock signal input 1
OEA, OEB Input LVCMOS Output enable
SEL0, SEL1 Input LVCMOS Clock switch select
QA[0-2], QA[0-2]
QB[0-2], QB[0-2]
Output LVPECL Differential clock outputs (banks A and B)
GND Supply GND Negative power supply
V
CC
Supply VCC Positive power supply. All V
CC
pins must be connected to the positive
power supply for correct DC and AC operation
Table 2. Function Table
Control Default 0 1
OEA 0 QA[0-2], Qx[0-2] are active. Deassertion of OE
can be asynchronous to the reference clock
without generation of output runt pulses
QA[0-2] = L, QA[0-2]
= H (outputs disabled). Assertion
of OE
can be asynchronous to the reference clock
without generation of output runt pulses
OEB
0 QA[0-2], Qx[0-2] are active. Deassertion of OE
can be asynchronous to the reference clock
without generation of output runt pulses
QA[0-2] = L, QA[0-2]
= H (outputs disabled). Assertion
of OE
can be asynchronous to the reference clock
without generation of output runt pulses
SEL0, SEL1 00 Refer to Table 4
Table 3. Clock Select Control
SEL0 SEL1 CLK0 Routed to CLK1 Routed to Application Mode
0 0 QA[0:2] and QB[0:2] 1:6 fanout of CLK0
0 1 QA[0:2] and QB[0:2] 1:6 fanout of CLK1
1 0 QA[0:2] QB[0:2] Dual 1:3 buffer
1 1 QB[0:2] QA[0:2] Dual 1:3 buffer (crossed)
Table 4. Absolute Maximum Ratings
(1)
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Symbol Characteristics Min Max Unit Condition
V
CC
Supply Voltage -0.3 3.6 V
V
IN
DC Input Voltage -0.3 V
CC
+0.3 V
V
OUT
DC Output Voltage -0.3 V
CC
+0.3 V
I
IN
DC Input Current 20 mA
I
OUT
DC Output Current 50 mA
T
S
Storage Temperature -65 125 C

MC100ES6254ACR2

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution FSL Differential LVP ECL 2x2 Clock Switch
Lifecycle:
New from this manufacturer.
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