MC100ES6254ACR2

MC100ES6254 REV. 7 JANUARY 7, 2013 7 ©2013 Integrated Device Technology, Inc.
MC100ES6254 Data Sheet 2.5/3.3V DIFFERENTIAL LVPECL 2X2 CLOCK SWITCH AND FANOUT BUFFER
APPLICATIONS INFORMATION
Example Configurations Understanding the Junction Temperature Range of the
MC100ES6254
To make the optimum use of high clock frequency and low
skew capabilities of the MC100ES6254, the MC100ES6254
is specified, characterized and tested for the junction
temperature range of T
J
= 0C to +110C. Because the exact
thermal performance depends on the PCB type, design,
thermal management and natural or forced air convection,
the junction temperature provides an exact way to correlate
the application specific conditions to the published
performance data of this data sheet. The correlation of the
junction temperature range to the application ambient
temperature range and vice versa can be done by
calculation:
T
J
= T
A
+ R
thja
P
tot
Assuming a thermal resistance (junction to ambient) of
54.4C/W (2s2p board, 200 ft/min airflow, refer to Table 8)
and a typical power consumption of 467mW (all outputs
terminated 50 to V
TT
, V
CC
= 3.3 V, frequency independent),
the junction temperature of the MC100ES6254 is
approximately T
A
+ 24.5C, and the minimum ambient
temperature in this example case calculates to –24.5C (the
maximum ambient temperature is 85.5C, refer to Table 8).
Exceeding the minimum junction temperature specification of
the MC100ES6254 does not have a significant impact on the
device functionality. However, the continuous use the
MC100ES6254 at high ambient temperatures requires
thermal management to not exceed the specified maximum
junction temperature. Refer to the Freescale application note
AN1545 for a power consumption calculation guideline.
Figure 4. MC100ES6254 AC Test Reference
Differential
Pulse Generator
Z = 50
R
T
= 50
Z
O
= 50
DUT
MC100ES6254
V
TT
R
T
= 50
Z
O
= 50
V
TT
2 x 2 CLOCK SWITCH
CLK0
CLK1
SEL0
SEL1
System A
System B
MC100ES6254
3
3
SEL0 SEL1 Switch Configuration
0 0 CLK0 clocks systems A and system B
0 1 CLK1 clocks system A and system B
1 0 CLK0 clocks system A and CLK1 clocks system B
1 1 CLK1 clocks system B and CLK1 clocks system A
1:6 CLOCK FANOUT BUFFER
CLK0
CLK1
SEL0
SEL1
MC100ES6254
0
0
LOOPBACK DEVICE
SEL0 SEL1 Switch Configuration
0 0 System loopback
0 1 Line loopback
1 0 Transmit/Receive operation
1 1 System and line loopback
CLK0
CLK1
SEL0
SEL1
Transmitter
Receiver
MC100ES6254
QA[]
System-Tx
System-Rx
QB[]
Table 8. Ambient Temperature Range (P
tot
= 467 mW)
R
thja
(2s2p board)
T
A, min
(1)
1. The MC100ES6254 device function is guaranteed from
T
A
= –40C to T
J
= 110C.
T
A, max
Natural Convection 59.0C/W –28C82C
100 ft/min 54.4C/W –25C85C
200 ft/min 52.5C/W –24.5C 85.5C
400 ft/min 50.4C/W –23.5C 86.5C
800 ft/min 47.8C/W –22C88C
MC100ES6254 REV. 7 JANUARY 7, 2013 8 ©2013 Integrated Device Technology, Inc.
MC100ES6254 Data Sheet 2.5/3.3V DIFFERENTIAL LVPECL 2X2 CLOCK SWITCH AND FANOUT BUFFER
Maintaining Lowest Device Skew
The MC100ES6254 guarantees low output-to-output bank
skew of 50 ps and a part-to-part skew of maximum 250 ps. To
ensure low skew clock signals in the application, both outputs
of any differential output pair need to be terminated
identically, even if only one output is used. When fewer than
all nine output pairs are used, identical termination of all
output pairs within the output bank is recommended. If an
entire output bank is not used, it is recommended to leave all
of these outputs open and unterminated. This will reduce the
device power consumption while maintaining minimum
output skew.
Power Supply Bypassing
The MC100ES6254 is a mixed analog/digital product. The
differential architecture of the MC100ES6254 supports low
noise signal operation at high frequencies. In order to
maintain its superior signal quality, all V
CC
pins should be
bypassed by high-frequency ceramic capacitors connected
to GND. If the spectral frequencies of the internally generated
switching noise on the supply pins cross the series resonant
point of an individual bypass capacitor, its overall impedance
begins to look inductive and thus increases with increasing
frequency. The parallel capacitor combination shown ensures
that a low impedance path to ground exists for frequencies
well above the noise bandwidth.
Figure 5. V
CC
Power Supply Bypass
V
CC
MC100ES6254
V
CC
33...100 nF 0.1 nF
MC100ES6254 REV. 7 JANUARY 7, 2013 9 ©2013 Integrated Device Technology, Inc.
MC100ES6254 Data Sheet 2.5/3.3V DIFFERENTIAL LVPECL 2X2 CLOCK SWITCH AND FANOUT BUFFER
PACKAGE DIMENSIONS
CASE 873A-04
ISSUE C
32-LEAD LQFP PACKAGE
PAGE 1 OF 3

MC100ES6254ACR2

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution FSL Differential LVP ECL 2x2 Clock Switch
Lifecycle:
New from this manufacturer.
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