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MC100ES6254ACR2

P1-P3P4-P6P7-P9P10-P12
MC100ES6254 REV. 7 JANUARY 7, 2013 4 ©2013 Integrated Device Technology, Inc.
MC100ES6254 Data Sheet 2.5/3.3V DIFFERENTIAL LVPECL 2X2 CLOCK SWITCH AND FANOUT BUFFER
Table 5. General Specifications
Symbol Characteristics Min Typ Max Unit Condition
V
TT
Output termination voltage V
CC
–2
(1)
1. Output termination voltage V
TT
= 0 V for V
CC
= 2.5 V operation is supported but the power consumption of the device will increase.
V
MM ESD Protection (Machine model) 200 V
HBM ESD Protection (Human body model) 2000 V
CDM ESD Protection (Charged device model) 1500 V
LU Latch-up immunity 200 mA
C
IN
4.0 pF Inputs
JA
Thermal resistance junction to ambient
JESD 51-3, single layer test board
JESD 51-6, 2S2P multilayer test board
83.1
73.3
68.9
63.8
57.4
59.0
54.4
52.5
50.4
47.8
86.0
75.4
70.9
65.3
59.6
60.6
55.7
53.8
51.5
48.8
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
JC
Thermal resistance junction to case 23.0 26.3 C/W MIL-SPEC 883E Method 1012.1
Operating junction temperature
(2)
(continuous operation) MTBF = 9.1 years
2. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according
to the application life time requirements (See application note AN1545 and the application section in this data sheet for more information).
The device AC and DC parameters are specified up to 110C junction temperature allowing the MC100ES6254 to be used in applications
requiring industrial temperature range. It is recommended that users of the MC100ES6254 employ thermal modeling analysis to assist in
applying the junction temperature specifications to their particular application.
110 C
T
Func
Functional temperature range T
A
= –40 T
J
= +110 C
MC100ES6254 REV. 7 JANUARY 7, 2013 5 ©2013 Integrated Device Technology, Inc.
MC100ES6254 Data Sheet 2.5/3.3V DIFFERENTIAL LVPECL 2X2 CLOCK SWITCH AND FANOUT BUFFER
Table 6. DC Characteristics (V
CC
= 3.3 V 5% or 2.5 V 5%, T
J
= 0 to +110C)
Symbol Characteristics Min Typ Max Unit Condition
LVCMOS Control Inputs (OEA, OEB, SEL0, SEL1)
V
IL
Input Voltage Low 0.8 V
V
IH
Input Voltage High 2.0 V
I
IN
Input Current
(1)
1. Inputs have internal pullup/pulldown resistors that affect the input current.
100 AV
IN
= V
CC
or V
IN
= GND
-+ Clock Inputs (CLK0, CLK0, CLK1, CLK1)
V
PP
AC differential input voltage
(2)
2. V
PP
is the minimum differential input voltage swing required to maintain AC characteristic.
0.1 1.3 V Differential operation
V
CMR
Differential cross point voltage
(3)
3. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
(DC)
range and the input swing lies within the V
PP
(DC) specification.
1.0 V
CC
–0.3 V Differential operation
LVPECL Clock Outputs (QA0–2, QA0–2, QB0–2, QB0–2)
V
OH
Output High Voltage V
CC
–1.2 V
CC
–1.005 V
CC
–0.7 V I
OH
= –30 mA
(4)
4. Equivalent to a termination 50 to V
TT
.
V
OL
Output Low Voltage V
CC
= 3.3 V5%
V
CC
= 2.5 V5%
V
CC
–1.9
V
CC
–1.9
V
CC
–1.705
V
CC
–1.705
V
CC
–1.5
V
CC
–1.3
VI
OL
= –5 mA
(5)
5. I
CC
calculation: I
CC
= (number of differential output pairs used) * (I
OH
+ I
OL
) + I
GND
I
CC
= (number of differential output pairs used) * (V
OH
-V
TT
)R
load
+(V
OL
-V
TT
)R
load
) + I
GND
Supply Current
I
GND
Maximum Quiescent Supply Current without
output termination current
52 85 mA GND pin
MC100ES6254 REV. 7 JANUARY 7, 2013 6 ©2013 Integrated Device Technology, Inc.
MC100ES6254 Data Sheet 2.5/3.3V DIFFERENTIAL LVPECL 2X2 CLOCK SWITCH AND FANOUT BUFFER
Table 7. AC Characteristics (V
CC
= 3.3 V 5% or 2.5 V 5%, T
J
= 0 to +110C)
(1)
1. AC characteristics apply for parallel output termination of 50 to V
TT
.
Symbol Characteristics Min Typ Max Unit Condition
V
PP
Differential Input Voltage
(2)
(peak-to-peak)
2. V
PP
is the minimum differential input voltage swing required to maintain AC characteristics including t
PD
and device-to-device skew.
0.3 1.3 V
V
CMR
Differential Input Crosspoint Voltage
(3)
3. V
CMR
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
CMR
(AC)
range and the input swing lies within the V
PP
(AC) specification. Violation of V
CMR
(AC) or V
PP
(AC) impacts the device propagation delay,
device and part-to-part skew.
1.2 V
CC
-0.3 V
V
O(P–P)
Differential Output Voltage (peak-to-peak)
f
O
< 1.1GHz
f
O
< 2.5GHz
f
O
< 3.0GHz
0.45
0.35
0.20
0.7
0.55
0.35
V
V
V
f
CLK
Input Frequency 0 3000
(4)
4. The MC100ES6254 is fully operational up to 3.0 GHz and is characterized up to 2.7GHz.
MHz
t
PD
Propagation Delay CLK, 1 to QA[] or QB[] 360 485 610 ps Differential
t
sk(O)
Output-to-Output Skew 50 ps Differential
t
sk(PP)
Output-to-Output Skew (part-to-part) 250 ps Differential
t
SK(P)
DC
O
Output Pulse Skew
(5)
Output Duty Cycle t
REF
< 100MHz
t
REF
< 800MHz
5. Output pulse skew is the absolute difference of the propagation delay times: | t
PLH
– t
PHL
|.
49.4
45.2
60
50.6
54.8
ps
%
%
DC
fref
= 50%
DC
fref
= 50%
t
JIT(CC)
Output Cycle-to-Cycle Jitter (SEL0 SEL1) TBD
t
r
, t
f
Output Rise/Fall Time 0.05 300 ps 20% to 80%
t
PDL
(6)
6. Propagation delay OE deassertion to differential output disabled (differential low: true output low, complementary output high).
Output Disable Time 2.5T + t
PD
3.5T + t
PD
ns T = CLK period
t
PLD
(7)
7. Propagation delay OE assertion to output enabled (active).
Output Enable Time 3T + t
PD
4T + t
PD
ns T = CLK period
Figure 3. MC100ES6254 Output Disable/Enable Timing
t
PDL
(OEX to Qx[])
50%
t
PLD
(OEX to Qx[])
Outputs Disabled
CLKX
CLKX
OEX
Qx[]
Qx[]
P1-P3P4-P6P7-P9P10-P12

MC100ES6254ACR2

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Buy MC100ES6254ACR2
Manufacturer:
IDT
Description:
Clock Drivers & Distribution FSL Differential LVP ECL 2x2 Clock Switch
Lifecycle:
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