LTC2862A
15
2862af
For more information www.linear.com/LTC2862A
High Receiver Input Resistance
The bus receiver input load from A or B to GND is less than
one-seventh unit load, permitting a total of 224 receivers
per system without exceeding the RS485 receiver loading
specification. The input load of the receiver is unaffected by
enabling/disabling the receiver or by powering/unpowering
the part.
Supply Current
The unloaded static supply currents in these devices
are low — typically 1.1mA for non slew limited devices
and 3.5mA for slew limited devices. In applications
with resistively terminated cables, the supply current is
dominated by the driver load. For example, when using two
120Ω terminators with a differential driver output voltage
of 2V, the DC load current is 33mA, which is sourced by
the positive voltage supply. Power supply current increases
with toggling data due to capacitive loading and this term
can increase significantly at high data rates. A plot of
the supply current vs data rate is shown in the Typical
Performance Characteristics of this data sheet.
During fault conditions with a positive voltage larger than
the supply voltage applied to the transmitter pins, or during
transmitter operation with a high positive common mode
voltage, positive current of up to 80mA may flow from the
transmitter pins back to V
CC
. If the system power supply
or loading cannot sink this excess current, a 5.6V 1W
1N4734 Zener diode may be placed between V
CC
and GND
to prevent an overvoltage condition on V
CC
.
The LTC2862A contains a supply undervoltage lockout
circuit that enables the transmitter and receiver outputs
when V
CC
exceeds ~2.7V and disables the transmitter and
receiver outputs when V
CC
falls below ~2.5V.
When the LTC2862A is unpowered, the logic inputs (DE,
DI, RE) are high impedance for voltages > 0V. Each input
has a diode clamp to GND that will conduct if a negative
voltage sufficient to forward bias the diode (~ –0.6V at
25°C) is applied to the pad. The RO output contains a CMOS
driver with parasitic diodes to GND and V
CC
. The diode to
GND will conduct if forward biased by a negative voltage
below GND, while the diode to V
CC
will conduct if forward
biased by a positive voltage above V
CC
. If V
CC
is low, this
applicaTions inForMaTion
will result in the RO line being clamped to approximately
0.6V above V
CC
. The impedance of the logic inputs and the
RO output are not tested with the LTC2862A unpowered.
Shutdown Mode Delay
The LTC2862A features a low power shutdown mode
that is entered when both the driver and the receiver
are simultaneously disabled (pin DE low and RE high).
A shutdown mode delay of approximately 250ns (not
tested in production) is imposed after this state is received
before the chip enters shutdown. If either DE goes high
or RE goes low during this delay, the delay timer is reset
and the chip does not enter shutdown. This reduces the
chance of accidentally entering shutdown if DE and RE are
driven in parallel by a slowly changing signal or if DE and
RE are driven by two independent signals with a timing
skew between them.
This shutdown mode delay does not affect the outputs of
the transmitter and receiver, which start to switch to the
high impedance state upon the reception of their respec-
tive disable signals as defined by the parameters t
SHDND
and t
SHDNR
. The shutdown mode delay affects only the
time when all the internal circuits that draw DC power
from V
CC
are turned off.
High Speed Considerations
A ground plane layout with a 0.1µF bypass capacitor placed
less than 7mm away from the V
CC
pin is recommended.
The PC board traces connected to signals A/B should be
symmetrical and as short as possible to maintain good
differential signal integrity. To minimize capacitive effects,
the differential signals should be separated by more than
the width of a trace and should not be routed on top of
each other if they are on different signal planes.
Care should be taken to route outputs away from any
sensitive inputs to reduce feedback effects that might
cause noise, jitter, or even oscillations.
The logic inputs have a typical hysteresis of 100mV to
provide noise immunity. Fast edges on the outputs can
cause glitches in the ground and power supplies which are
exacerbated by capacitive loading. If a logic input is held
near its threshold (typically V
CC
/2), a noise glitch from a
