MAX8855ETJ+T Datasheet MAX8855AETJ+T, MAX8855AETJ+, MAX8855ETJ+ | P10-P12

The power-good, open-drain output for regulator 2

(PWRGD2) is high impedance when V

SS2

≥ 0.54V and

FB2

≥ 0.9 x V

SS2

. PWRGD2 is low when V

SS2

< 0.54V,

EN2 is low, V

VDD

or V

IN2

is below V

UVLO

, the thermal-over-

load protection is activated, or when V

FB2

< 0.9 x V

SS2

External Reference Input (REFIN)

The MAX8855/MAX8855A have an external reference

input. Connect an external reference between 0 and

VDD

- 1.6V to REFIN to set the FB1 regulation voltage.

To use the internal 0.6V reference, connect REFIN to

SS1. When the IC is shut down, REFIN is pulled to GND

through 335Ω.

Startup and Sequencing

The MAX8855/MAX8855A feature separate enable

inputs (EN1 and EN2) for the two regulators. Driving

EN_ high enables the corresponding regulator; driving

EN_ low turns the regulator off. Driving both EN1 and

EN2 low puts the IC in low-power shutdown mode,

reducing the supply current typically to 30nA. The

MAX8855/MAX8855A regulators power up when the fol-

lowing conditions are met (see Figure 2):

• EN_ is logic-high.

•V

VDD

is above the UVLO threshold.

•V

IN_

is above the UVLO threshold.

• The internal reference is powered.

• The IC is not in thermal overload (T

< +165°C).

Once these conditions are met, the MAX8855/

MAX8855A begin soft-start. FB2 regulates to the volt-

age at SS2. During soft-start, the SS2 capacitor is

charged with a constant 8μA current source so that its

voltage ramps up for the soft-start time. See the

Setting

the Soft-Start Time

section to select the SS2 capacitor

for the desired soft-start time. FB1 regulates to the volt-

age at REFIN. Connect REFIN to SS1 to use the internal

MAX8855/MAX8855A

Dual, 5A, 2MHz Step-Down Regulators

10 ______________________________________________________________________________________

Figure 2. Startup Control Diagram

UVLO

THERM

SHDN

THERM

SHDN

REF

BIAS

GEN

REF

RDY

UVLO

RRUVB

EN1

EN2

REG1 ON

REG2 ON

UVLO

TLIM

IN1

IN2

Figure 3a. Startup and Sequencing Options—Two Independent Output Startup and Shutdown Waveforms

EN1

SS2

PWRGD1

EN1

OUT1

OUT2

PWRGD2

EN2

SS1

PWRGD2

REFIN

EN2

PWRGD1

10kΩ

EN1

MAX8855/MAX8855A

Dual, 5A, 2MHz Step-Down Regulators

______________________________________________________________________________________ 11

Figure 3b. Startup and Sequencing Options—Ratiometric Tracking Startup and Shutdown Waveforms V

OUT1

Track V

OUT2

OUT1

PWRGD1

PWRGD2

OUT2

EN1

SS2

PWRGD1

EN2

SS1

PWRGD2

REFIN

10kΩ

10kΩ 10kΩ

reference with soft-start time set independently by the

SS1 capacitor (see Figure 3a).

For ratiometric tracking applications, connect REFIN to

the center of a voltage-divider from the output of regula-

tor 2 to GND (see Figure 3b). In this application, the EN_

inputs are connected to each other and driven as a sin-

gle enable input. Regulator 2 starts up with a normal soft-

start (C

SS2

sets the time), and regulator 1 output

ratiometrically tracks the regulator 2 output voltage. The

voltage-divider resistors set the V

OUT1

OUT2

ratio (see

the

Setting the Output Voltage

section). In Figure 3b,

OUT1

regulates to half of V

OUT2

. Note that a capaci-

tance of 1000pF should be connected to SS1 for stability.

Figure 3c shows the output sequencing application

using an external reference.

Figure 3c. Startup and Sequencing Options—Sequencing Startup and Shutdown Waveforms with External Reference

EN1

OUT1

OUT2

PWRGD2

PWRGD1

EN1

SS2

PWRGD1

EN2

SS1

PWRGD2

REFIN

10kΩ

EN1

Sequencing is achieved by connecting EN2 to

PWRGD1. In this mode, regulator 2 starts once regulator

1 reaches regulation.

In Figure 3d, EN1 and EN2 are connected together and

driven as a single input. Although both outputs begin

ramping up at the same time, slope matching is

achieved by selecting the SS_ capacitors. See the

Setting the Soft-Start Time

section for information on

selecting the SS_ capacitors. In Figure 3d, the slope of

the output voltages during soft-start is equal. This is

achieved by setting the ratio of the soft-start capacitors

equal to the ratio of the output voltages:

Synchronization (FSYNC)

The MAX8855/MAX8855A operate from 500kHz to

2MHz using either its internal oscillator, or an externally

supplied clock. See the

Setting the Switching

Frequency

section.

Thermal-Overload Protection

Thermal-overload protection limits the total power dissi-

pation of the MAX8855/MAX8855A. Internal thermal sen-

sors monitor the junction temperature at each of the

regulators. When the junction temperature exceeds

+165°C, the corresponding regulator is shut down,

allowing the IC to cool. The thermal sensor turns the reg-

ulator on after the junction temperature cools by +20°C.

In a continuous thermal-overload condition, this results in

a pulsed output.

Design Procedure

Setting the Output Voltage

The output voltages for regulator 1 (with REFIN con-

nected to SS1) and regulator 2 are set with a resistor

voltage-divider connected from the output to FB_ to

GND as shown in Figure 4. Select a value for the resis-

tor connected from output to FB_ (R4 in Figure 4)

between 2kΩ and 10kΩ. Use the following equations to

find the value for the resistor connected from FB_ to

GND (R6 in Figure 4):

OUT

−

()

OUT

MAX8855/MAX8855A

Dual, 5A, 2MHz Step-Down Regulators

12 ______________________________________________________________________________________

Figure 3d. Startup and Sequencing Options—Matching Startup Slopes of Output Voltages with Internal Reference

OUT1

OUT2

PWRGD2

PWRGD1

EN1

SS2

PWRGD1

EN2

SS1

PWRGD2

REFIN

10kΩ

Figure 4. Type III Compensation Network

LX_

FB_

COMP_

C11

OUTPUT

C10

MAX8855/

MAX8855A

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

MAX8855ETJ+T

Mfr. #:

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Manufacturer:

Maxim Integrated

Description:

Switching Voltage Regulators Dual 5A 2MHz Step-Down Regulator

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