MAX8855/MAX8855A
Dual, 5A, 2MHz Step-Down Regulators
______________________________________________________________________________________ 13
In DDR tracking applications such as Figure 7, the FB1
regulation voltage tracks the voltage at REFIN. In Figure
7, the output of regulator 1 tracks V
OUT2
, and the ratio
of the output voltages is set as follows:
Setting the Switching Frequency
The MAX8855/MAX8855A have an adjustable internal
oscillator that can be set to any frequency from 500kHz
to 2MHz. To set the switching frequency, connect a
resistor from FSYNC to GND. Calculate the resistor
value from the following equation:
The MAX8855/MAX8855A can also be synchronized to
an external clock from 500kHz to 2MHz by connecting
the clock signal to FSYNC through a 10kΩ isolation
resistor. The external sync frequency must be higher
than the frequency that would be produced by R
FSYNC
.
The two regulators switch at the same frequency as the
FSYNC clock, and are 180° out-of-phase with each
other. The external clock duty cycle may range
between 10% and 90% to ensure 180° out-of-phase
operation.
Setting the Soft-Start Time
The two step-down regulators have independent
adjustable soft-start. Capacitors from SS_ to GND are
charged from a constant 8μA (typ) current source to the
feedback-regulation voltage. The value of the soft-start
capacitors is calculated from the desired soft-start time
as follows:
Inductor Selection
There are several parameters that must be examined
when determining which inductor to use: maximum
input voltage, output voltage, load current, switching
frequency, and LIR. LIR is the ratio of inductor current
ripple to DC load current. A higher LIR value allows for
a smaller inductor, but results in higher losses and
higher output ripple. On the other hand, higher inductor
values increase efficiency, but eventually resistive loss-
es due to extra turns of wire exceed the benefit gained
from lower AC current levels. A good compromise
between size and efficiency is a 30% LIR. For applica-
tions in which size and transient response are impor-
tant, an LIR of around 40% to 50% is recommended.
Once all the parameters are chosen, the inductor value
is determined as follows:
where f
S
is the switching frequency. Choose a standard
value close to the calculated value. The exact inductor
value is not critical and can be adjusted to make trade-
offs among size, cost, and efficiency. Find a low-loss
inductor with the lowest possible DC resistance that fits
the allotted dimensions. The peak inductor current is
determined as:
I
PEAK
must not exceed the chosen inductor’s saturation
current rating or the minimum current-limit specification
for the MAX8855/MAX8855A.
Input-Capacitor Selection
The input capacitor for each regulator serves to reduce
the current peaks drawn from the input power supply
and reduces switching noise in the IC. The total input
capacitance for each rail must be equal to or greater
than the value given by the following equation to keep
the input-voltage ripple within specifications and mini-
mize the high-frequency ripple current being fed back
to the input source:
where D_ is the quiescent duty cycle (V
OUT_
/V
IN_
); f
SW
is the switching frequency; and V
IN_RIPPLE_
is the
peak-to-peak input-ripple voltage, which should be less
than 2% of the minimum DC input voltage.
The impedance of the input capacitor at the switching
frequency should be less than that of the input source
so high-frequency switching currents do not pass
through the input source but are instead shunted
through the input capacitor. High source impedance
requires high-input capacitance. The input capacitor
must meet the ripple current requirement imposed by
the switching currents. The RMS input ripple current,
I
RIPPLE_
, is given by:
IIDD
RIPPLE OUT__
_( _)×1
C
DI
fV
IN MIN
OUT
SW IN RIPPLE
__
_
__
_
=
×
×
I
LIR
I
PEAK OUT MAX
=+
×1
2
()
L
VVV
f V LIR I
OUT IN OUT
S IN OUT MAX
=
×−
()
×××
()
Ct
A
V
SS SS_
.
8
06
μ
R
f
ns
k
ns
FSYNC
S
=−
1
50
10
950
Ω
V
V
R
RR
OUT
OUT
1
2
19
119
=
+
Output-Capacitor Selection
The key selection parameters for the output capacitor
are capacitance, ESR, ESL, and voltage-rating require-
ments. These affect the overall stability, output ripple
voltage, and transient response of the DC-DC convert-
er. The output ripple occurs due to variations in the
charge stored in the output capacitor, the voltage drop
due to the capacitor’s ESR, and the voltage drop due to
the capacitor’s ESL. Calculate the output-voltage ripple
due to the output capacitance, ESR, and ESL as:
where the output ripple due to output capacitance,
ESR, and ESL is:
or:
whichever is greater.
It should be noted that the above ripple voltage compo-
nents add vectrorially rather than algebraically, thus
making V
RIPPLE
a conservative estimate.
The peak inductor current (I
P-P
) is:
Use these equations for initial capacitor selection.
Determine final values by testing a prototype or an eval-
uation circuit. A smaller ripple current results in less out-
put-voltage ripple. Since the inductor ripple current is a
function of the inductor value, the output-voltage ripple
decreases with larger inductance. Use ceramic capaci-
tors for low ESR and low ESL at the switching frequency
of the converter. The low ESL of ceramic capacitors
makes ripple voltages due to ESL negligible.
Load-transient response depends on the selected out-
put capacitance. During a load transient, the output
instantly changes by ESR x ΔI
LOAD
. Before the con-
troller can respond, the output deviates further,
depending on the inductor and output capacitor values.
After a short time, the controller responds by regulating
the output voltage back to its predetermined value. The
controller response time depends on the closed-loop
bandwidth. A higher bandwidth yields a faster
response time, preventing the output from deviating fur-
ther from its regulating value. See the
Compensation
Design
and
Safe-Starting into a Prebiased Output
sec-
tions for more details.
Compensation Design
The power-stage transfer function consists of one dou-
ble pole and one zero. The double pole is introduced
by the output filtering inductor, L, and the output filter-
ing capacitor, C
O
. The ESR of the output filtering
capacitor determines the zero. The double pole and
zero frequencies are given as follows:
where R
L
is equal to the sum of the output inductor’s
DC resistance and the internal switch resistance,
R
DS(ON)
. A typical value for R
DS(ON)
is 35mΩ. R
O
is the
output load resistance, which is equal to the rated out-
put voltage divided by the rated output current. ESR is
the total ESR of the output-filtering capacitor. If there is
more than one output capacitor of the same type in par-
allel, the value of the ESR in the above equation is
equal to that of the ESR of a single-output capacitor
divided by the total number of output capacitors.
The high-switching-frequency range of the MAX8855/
MAX8855A allows the use of ceramic output capacitors.
Since the ESR of ceramic capacitors is typically very
low, the frequency of the associated transfer-function
zero is higher than the unity-gain crossover frequency,
f
C
, and the zero cannot be used to compensate for the
double pole created by the output filtering inductor and
capacitor. The double pole produces a gain drop of
40dB and a phase shift of 180° per decade. The error
amplifier must compensate for this gain drop and phase
shift to achieve a stable high-bandwidth closed-loop
system. Therefore, use type III compensation as shown
in Figure 4. Type III compensation possesses three
poles and two zeros with the first pole, f
P1_EA
, located at
0Hz (DC). Locations of other poles and zeros of type III
compensation are given by:
f
RC
ZEA1
1
279
_
=
××π
f
ESR C
Z ESR
O
_
=
××
1
2π
ff
LC
R ESR
RR
PLC P LC
O
O
OL
12
1
2
__
==
×× ×
+
+
π
I
VV
fL
V
V
PP
IN OUT
S
OUT
IN
=
×
×
V
I
t
ESL
RIPPLE ESL
PP
OFF
()
V
I
t
ESL
RIPPLE ESL
PP
ON
()
V I ESR
RIPPLE ESR P P()
V
I
Cf
RIPPLE C
PP
OUT S
()
=
××
8
VV V V
RIPPLE RIPPLE C RIPPLE ESR RIPPLE ESL
=+ +
() ( ) ( )
MAX8855/MAX8855A
Dual, 5A, 2MHz Step-Down Regulators
14 ______________________________________________________________________________________
MAX8855/MAX8855A
Dual, 5A, 2MHz Step-Down Regulators
______________________________________________________________________________________ 15
These equations are based on the assumptions that C9
>> C10, and R4 >> R8, which are true in most applica-
tions. Placement of these poles and zeros is deter-
mined by the frequencies of the double pole and ESR
zero of the power stage transfer function. It is also a
function of the desired closed-loop bandwidth. Figure 5
shows the pole zero cancellations in the type III com-
pensation design.
The following section outlines the step-by-step design
procedure to calculate the required compensation com-
ponents. Begin by setting the desired output voltage as
described in the
Setting the Output Voltage
section.
The crossover frequency f
C
(or closed-loop, unity-gain
bandwidth of the regulator) should be between 10%
and 20% of the switching frequency, f
S
. A higher
crossover frequency results in a faster transient
response. Too high of a crossover frequency can result
in instability. Once f
C
is chosen, calculate C9 (in farads)
from the following equation:
where V
IN
is the input voltage in volts, f
C
is the
crossover frequency in Hertz, R4 is the upper feedback
resistor (in ohms), R
L
is the sum of the inductor resis-
tance and the internal switch on-resistance, and R
O
is
the output load resistance (V
OUT
/I
OUT
).
Due to the underdamped nature of the output LC double
pole, set the two zero frequencies of the type III com-
pensation less than the LC double-pole frequency to
provide adequate phase boost. Set the two zero fre-
quencies to 80% of the LC double-pole frequency.
Hence:
Set the third compensation pole, f
P3_EA
, at f
Z_ESR
,
which yields:
R
C ESR
C
O
8
11
=
×
C
R
L C R ESR
RR
OO
LO
11
1
08 4
=
×
×
×× +
()
+.
R
C
L C R ESR
RR
OO
LO
7
1
08 9
=
×
×
×× +
()
+.
C
V
fR
R
R
IN
C
L
O
9
25
241
=
×
×× ×+
.
π
f
RC
PEA3
1
2811
_
=
××π
f
RC
PEA2
1
2710
_
=
××π
f
RC
ZEA2
1
2411
_
=
××π
Figure 5. Pole Zero Cancellations in Compensation Design
OPEN-LOOP GAIN
DOUBLE POLES
THIRD POLE
SECOND POLE
FIRST AND SECOND ZEROS
POWER-STAGE TRANSFER FUNCTION
COMPENSATION TRANSFER FUNCTION
FREQUENCY
GAIN

MAX8855ETJ+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Switching Voltage Regulators Dual 5A 2MHz Step-Down Regulator
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet