MAX8855/MAX8855A
Set the second compensation pole at 1/2 the switching
frequency. Calculate C10 as follows:
The recommended range for R4 is 2kΩ to 10kΩ. Note
that the loop compensation remains unchanged if only
R6’s resistance is altered to set different outputs.
Safe-Starting into a Prebiased Output
The MAX8855/MAX8855A are capable of safe-starting
up into a prebiased output without discharging the out-
put capacitor. This type of operation is also termed
monotonic startup. However, in order to avoid output
voltage glitches during safe-start it should be ensured
that the inductor current is in continuous conduction
mode during the end of the soft-start period, this is
done by satisfying the following equation:
where C
O
is the output capacitor, V
O
is the output volt-
age, t
SS
is the soft-start time set by the soft-start capac-
itor C
SS
, and I
P-P
is the peak inductor ripple current (as
defined in the
Output-Capacitor Selection
section).
Depending on the application, one of these parameters
may drive the selection of the others. See Starting into
Prebiased Output waveforms in the
Typical Operating
Characteristics
section for an example selection of the
above parameters.
Applications Information
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. The switching
power stage requires particular attention. It is highly
recommended to duplicate the MAX8855 EV kit layout
for optimum performance. If deviation is necessary, fol-
low these guidelines for a good PCB layout:
• A multilayer PCB is recommended. Use inner-layer
ground (and power) planes to minimize noise coupling.
• Place the input ceramic decoupling capacitor
directly across and as close as possible to IN_ and
PGND_. This is to help contain the high switching
currents within a small loop.
• Connect IN_ and PGND_ separately to large copper
areas to help cool the IC and further improve effi-
ciency and long-term reliability.
• Connect input, output, and VDL capacitors to the
power ground plane (PGND_).
• Keep the path of switching currents short and mini-
mize the loop area formed by LX_, the output
capacitor(s), and the input capacitor(s).
• Place the IC decoupling capacitors as close as
possible to the IC pins, connecting all other ground-
terminated capacitors, resistors, and passive com-
ponents to the reference or analog ground plane
(GND).
• Separate the power and analog ground planes,
using a single-point common connection point (typi-
cally, at the C
IN_
cathode.
• Connect the exposed pad to the analog ground
plane, allowing sufficient copper area to help cool
the device. If the exposed pad is used as a com-
mon PGND_-to-GND connection point, avoid run-
ning high current through the exposed pad by
using separate vias to connect the PGND_ pins to
the power ground plane rather than connecting
them to the exposed pad on the top layer.
• Use caution when routing feedback and compensa-
tion node traces; avoid routing near high dV/dt
nodes (LX_) and high-current paths. Place the feed-
back and compensation components as close as
possible to the IC pins.
• Reference the MAX8855 Evaluation Kit for an exam-
ple layout.
