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LTC3404MPMS8#TRPBF

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10
LTC3404
3404fb
V
FB
GND
LTC3404
0.8V ≤ V
OUT
≤ 6V
R2
R1
3404 F03
Figure 3. Setting the LTC3404 Output Voltage
APPLICATIO S I FOR ATIO
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inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
Kool Mμ (from Magnetics, Inc.) is a very good, low loss
core material for toroids with a “soft” saturation character-
istic. Molypermalloy is slightly more efficient at high
(>200kHz) switching frequencies but quite a bit more
expensive. Toroids are very space efficient, especially
when you can use several layers of wire, while inductors
wound on bobbins are generally easier to surface mount.
New designs for surface mount inductors are available
from Coiltronics, Coilcraft, Dale and Sumida.
C
IN
and C
OUT
Selection
In continuous mode, the source current of the top MOS-
FET is a square wave of duty cycle V
OUT
/V
IN
. To prevent
large voltage transients, a low ESR input capacitor sized
for the maximum RMS current must be used. The maxi-
mum RMS capacitor current is given by:
CI
VVV
V
IN OMAX
OUT IN OUT
IN
required I
RMS
≅
−
()
[]
12/
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT
/2. This simple worst-case condition is com-
monly used for design because even significant deviations
do not offer much relief. Note that the capacitor
manufacturer’s ripple current ratings are often based on
2000 hours of life. This makes it advisable to further derate
the capacitor, or choose a capacitor rated at a higher
temperature than required. Several capacitors may also be
paralleled to meet size or height requirements in the
design. Always consult the manufacturer if there is any
question.
The selection of C
OUT
is driven by the required effective
series resistance (ESR). Typically, once the ESR require-
ment is satisfied, the capacitance is adequate for filtering.
The output ripple ΔV
OUT
is determined by:
Δ≅Δ +
⎛
⎝
⎜
⎞
⎠
⎟
V I ESR
fC
OUT L
OUT
1
8
where f = operating frequency, C
OUT
= output capacitance
and ΔI
L
= ripple current in the inductor. The output ripple
is highest at maximum input voltage since ΔI
L
increases
with input voltage. For the LTC3404, the general rule for
proper operation is:
C
OUT
required ESR < 0.25Ω
The choice of using a smaller output capacitance
increases the output ripple voltage due to the frequency
dependent term but can be compensated for by using
capacitor(s) of very low ESR to maintain low ripple
voltage. The I
TH
pin compensation components can be
opti
mized to provide stable high performance transient
response regardless of the output capacitor selected.
ESR is a direct function of the volume of the capacitor.
Manufacturers such as Taiyo-Yuden, AVX, Kemet, Sprague
and Sanyo should be considered for high performance
capacitors. The POSCAP solid electrolytic chip capacitor
available from Sanyo is an excellent choice for output bulk
capacitors due to its low ESR/size ratio. Once the ESR
requirement for C
OUT
has been met, the RMS current
rating generally far exceeds the I
RIPPLE(P-P)
requirement.
When using tantalum capacitors, it is critical that they are
surge tested for use in switching power supplies. A good
choice is the AVX TPS series of surface mount tantalum,
available in case heights ranging from 2mm to 4mm. Other
capacitor types include KEMET T510 and T495 series and
Sprague 593D and 595D series. Consult the manufacturer
for other specific recommendations.
Output Voltage Programming
The output voltage is set by a resistive divider according
to the following formula:
VV
R
R
OUT
=+
⎛
⎝
⎜
⎞
⎠
⎟
08 1
2
1
.
(2)
The external resistive divider is connected to the output,
allowing remote voltage sensing as shown in Figure 3.
11
LTC3404
3404fb
APPLICATIO S I FOR ATIO
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Figure 5. Phase-Locked Loop Block Diagram
SYNC/
MODE
PHASE
DETECTOR
DIGITAL
PHASE/
FREQUENCY
DETECTOR
2.4V
R
LP
C
LP
VCO
3404 F05
PLL LPF
Figure 4. Relationship Between Oscillator
Frequency and Voltage at PLL LPF Pin
V
PPL LPF
(V)
0.4
OSCILLATOR FREQUENCY (MHz)
1.6
3404 • F04
0.8 1.2 2.0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.6 1.0 1.4 1.8
Phase-Locked Loop and Frequency Synchronization
The LTC3404 has an internal voltage-controlled oscillator
and phase detector comprising a phase-locked loop. This
allows the top MOSFET turn-on to be locked to the rising
edge of an external frequency source. The frequency range
of the voltage-controlled oscillator is 1MHz to 1.7MHz. The
phase detector used is an edge sensitive digital type that
provides zero degrees phase shift between the
external and internal oscillators. This type of phase detec-
tor will not lock up on input frequencies close to the har-
monics of the V
CO
center frequency. The PLL hold-in range
Δf
H
is equal to the capture range, Δf
H
= Δf
C
= 300kHz and
–400kHz.
The output of the phase detector is a pair of complemen-
tary current sources charging or discharging the external
filter network on the PLL LPF pin. The relationship
between the voltage on the PLL LPF pin and operating
frequency is shown in Figure 4. A simplified block diagram
is shown in Figure 5.
If the external frequency (V
SYNC/MODE
) is greater than
1.4MHz, the center frequency, current is sourced
continuously, pulling up the PLL LPF pin. When the
external frequency is less than 1.4MHz, current is sunk
continuously, pulling down the PLL LPF pin. If the
external and internal frequencies are the same but exhibit
a phase difference, the current sources turn on for an
amount of time corresponding to the phase difference.
Thus the voltage on the PLL LPF pin is adjusted until the
phase and frequency of the external and internal oscilla-
tors are identical. At this stable operating point the phase
comparator output is high impedance and the filter
capacitor C
LP
holds the voltage.
The loop filter components C
LP
and R
LP
smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
component’s C
LP
and R
LP
determine how fast the loop
acquires lock. Typically R
LP
= 10k and C
LP
is 2200pF to
0.01μF. When not synchronized to an external clock, the
internal connection to the VCO is disconnected. This
disallows setting the internal oscillator frequency by a DC
voltage on the V
PLL LPF
pin.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC3404 circuits: V
IN
quiescent current and I
2
R
losses. The V
IN
quiescent current loss dominates the
efficiency loss at very low load currents whereas the I
2
R
loss dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
12
LTC3404
3404fb
LOAD CURRENT (mA)
0.1 1
0.00001
POWER LOST (W)
0.001
1
10 100 1000
3404 F06
0.0001
0.01
0.1
V
OUT
= 1.5V
V
OUT
= 2.5V
V
OUT
= 3.3V
V
IN
= 4.2V
L = 4.7μH
Burst Mode OPERATION
Figure 6. Power Lost vs Load Current
APPLICATIO S I FOR ATIO
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very low load currents can be misleading since the actual
power lost is of no consequence as illustrated in Figure 6.
1. The V
IN
quiescent current is due to two components:
the DC bias current as given in the electrical character-
istics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge dQ moves from V
IN
to ground. The resulting
dQ/dt is the current out of V
IN
that is typically larger than
the DC bias current. In continuous mode, I
GATECHG
=
f(Q
T
+ Q
B
) where Q
T
and Q
B
are the gate charges of the
internal top and bottom switches. Both the DC bias and
gate charge losses are proportional to V
IN
and thus
their effects will be more pronounced at higher supply
voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor R
L
. In
continuous mode the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R
DS(ON)
and the duty cycle
(DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Charateristics
curves. Thus, to obtain I
2
R losses, simply add R
SW
to
R
L
and multiply the result by the square of the average
output current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for less
than 2% total additional loss.
Thermal Considerations
In most applications the LTC3404 does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC3404 is running at high ambient tempera-
ture with low supply voltage and high duty cycles, such
as in dropout, the heat dissipated may exceed the maxi-
mum junction temperature of the part. If the junction
temperature reaches approximately 175°C, both power
switches will be turned off and the SW node will become
high impedance.
To avoid the LTC3404 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
T
R
= (P
D
)(θ
JA
)
where P
D
is the power dissipated by the regulator and q
JA
is the thermal resistance from the junction of the die to the
ambient temperature.
The junction temperature, T
J
, is given by:
T
J
= T
A
+ T
R
where T
A
is the ambient temperature.
As an example, consider the LTC3404 in dropout at an
input voltage of 3V, a load current of 500mA, and an
ambient temperature of 70°C. From the typical perfor-
mance graph of switch resistance, the R
DS(ON)
of the
P-channel switch at 70°C is approximately 0.7Ω. There-
fore, power dissipated by the part is:
P
D
= I
LOAD
2
• R
DS(ON)
= 0.175W
For the MSOP package, the θ
JA
is 150°C/ W. Thus, the
junction temperature of the regulator is:
T
J
= 70°C + (0.175)(150) = 96°C
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LTC3404MPMS8#TRPBF

Mfr. #:
Buy LTC3404MPMS8#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Military Plastic: 600mA, 1.4MHz Synch Buck Reg
Lifecycle:
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