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PCF8576DU/2DA/2,02

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P59
PCF8576D All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 15 — 12 February 2015 34 of 59
NXP Semiconductors
PCF8576D
40 × 4 universal LCD driver for low multiplex rates
13. Dynamic characteristics
[1] Typical output duty factor: 50 % measured at the CLK output pin.
[2] Not tested in production.
[3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to V
IL
and V
IH
with an
input voltage swing of V
SS
to V
DD
.
Table 20. Dynamic characteristics
V
DD
= 1.8 V to 5.5 V; V
SS
= 0 V; V
LCD
= 2.5 V to 6.5 V; T
amb
=
40
C to +85
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Clock
f
clk(int)
internal clock frequency
[1]
1440 1850 2640 Hz
f
clk(ext)
external clock frequency 960 - 2640 Hz
t
clk(H)
HIGH-level clock time 60 - - s
t
clk(L)
LOW-level clock time 60 - - s
Synchronization
t
PD(SYNC_N)
SYNC propagation delay - 30 - ns
t
SYNC_NL
SYNC LOW time 1 - - s
t
PD(drv)
driver propagation delay V
LCD
= 5 V
[2]
--30s
I
2
C-bus
[3]
Pin SCL
f
SCL
SCL clock frequency - - 400 kHz
t
LOW
LOW period of the SCL
clock
1.3 - - s
t
HIGH
HIGH period of the SCL
clock
0.6 - - s
Pin SDA
t
SU;DAT
data set-up time 100 - - ns
t
HD;DAT
data hold time 0 - - ns
Pins SCL and SDA
t
BUF
bus free time between a
STOP and START
condition
1.3 - - s
t
SU;STO
set-up time for STOP
condition
0.6 - - s
t
HD;STA
hold time (repeated)
START condition
0.6 - - s
t
SU;STA
set-up time for a repeated
START condition
0.6 - - s
t
r
rise time of both SDA and
SCL signals
f
SCL
= 400 kHz - - 0.3 s
f
SCL
< 125 kHz - - 1.0 s
t
f
fall time of both SDA and
SCL signals
--0.3s
C
b
capacitive load for each
bus line
--400pF
t
w(spike)
spike pulse width on the I
2
C-bus - - 50 ns
PCF8576D All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 15 — 12 February 2015 35 of 59
NXP Semiconductors
PCF8576D
40 × 4 universal LCD driver for low multiplex rates
14. Application information
14.1 Cascaded operation
In large display configurations, up to 16 PCF8576Ds can be differentiated on the same
I
2
C-bus by using the 3-bit hardware subaddresses (A0, A1 and A2) and the
programmable I
2
C-bus slave address (SA0).
Fig 21. Driver timing waveforms
Fig 22. I
2
C-bus timing waveforms
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PCF8576D All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 15 — 12 February 2015 36 of 59
NXP Semiconductors
PCF8576D
40 × 4 universal LCD driver for low multiplex rates
PCF8576Ds connected in cascade are synchronized to allow the backplane signals from
only one device in the cascade to be shared. This arrangement is cost-effective in large
LCD applications since the backplane outputs of only one device need to be
through-plated to the backplane electrodes of the display. The other PCF8576D of the
cascade contribute additional segment outputs. The backplanes can either be connected
together to enhance the drive capability or some can be left open-circuit (such as the ones
from the slave in Figure 23
) or just some of the master and some of the slave will be taken
to facilitate the layout of the display.
All PCF8576Ds connected in cascade are correctly synchronized by the SYNC
signal.
This synchronization is guaranteed after the power-on reset. The only time that SYNC
is
likely to be needed is if synchronization is lost accidentally, for example, by noise in
adverse electrical environments, or if the LCD multiplex drive mode is changed in an
application using several cascaded PCF8576Ds, as the drive mode cannot be changed
on all of the cascaded devices simultaneously. SYNC
can be either an input or an output
signal; a SYNC
output is implemented as an open-drain driver with an internal pull-up
resistor. The PCF8576D asserts SYNC
at the start of its last active backplane signal and
monitors the SYNC
line at all other times. If cascade synchronization is lost, it is restored
by the first PCF8576D to assert SYNC
. The timing relationship between the backplane
waveforms and the SYNC
signal for each LCD drive mode is shown in Figure 24.
The contact resistance between the SYNC
on each cascaded device must be controlled.
If the resistance is too high, the device is not able to synchronize properly; this is
particularly applicable to chip-on-glass applications. The maximum SYNC
contact
resistance allowed for the number of devices in cascade is given in Table 22
.
Table 21. Addressing cascaded PCF8576D
Cluster Bit SA0 Pin A2 Pin A1 Pin A0 Device
100000
0011
0102
0113
1004
1015
1106
1117
210008
0019
01010
01111
10012
10113
11014
11115
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P59

PCF8576DU/2DA/2,02

Mfr. #:
Buy PCF8576DU/2DA/2,02
Manufacturer:
NXP Semiconductors
Description:
LCD Drivers PCF8576DU/WLCSP59//2DA/2/DIE 2 WAFFLE CARRIERS ND
Lifecycle:
New from this manufacturer.
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