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NCP81246MNTXG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
NCP81246
www.onsemi.com
16
Interleaving
In order to minimize stress on the input voltage and
simplify input filter design, the NCP81246 monitors the
phase-angle relationship between the rails used for Rail1
and Rail2. Small adjustments are made to keep phases of
both rails from turning on at the same time. Priority is given
to transient response, i.e. if a phase must turn on to respond
to a load increase, the phase will not be gated if the other rail
has a phase that is turned on. The feature is intended to
reduce loading on the input rail during steady-state
conditions. If either rail is operating in DCM mode, this
feature will be disabled.
Ultra-Sonic Mode
Ultra-Sonic Mode forces a minimum switching frequency
above audible range when a rail is in DCM mode.
Two-Phase Rail Voltage Compensation
The remote Sense Amplifier output is applied to a Type III
compensation network formed by the error amplifier and
external tuning components. The non-inverting input of the
error amplifier is connected to the same reference voltage
used to bias the Remote sense amplifier output.
Two-Phase Rail Remote Sense Amplifier
A high performance high input impedance true
differential amplifier is provided to accurately sense the
output voltage of the regulator. The VSP and VSN inputs
should be connected to the regulator’s output voltage sense
points. The remote sense amplifier takes the difference of
the output voltage with the DAC voltage and adds the droop
voltage to
V
DIFFOUT
+
ǒ
V
VSP
* V
VSN
Ǔ
)
ǒ
1.3 V * V
DAC
Ǔ
)
(eq. 1)
)
ǒ
V
DROOP
* V
CSREF
Ǔ
This signal then goes through a standard error
compensation network and into the inverting input of the
error amplifier. The non-inverting input of the error
amplifier is connected to the same 1.3 V reference used for
the differential sense amplifier output bias.
Two-Phase Rail High Performance Voltage Error
Amplifier
A high performance error amplifier is provided for high
bandwidth transient performance. A standard type III
compensation circuit is normally used to compensate the
system.
Figure 7. Standard Type III Compensation Circuit
−
+
C
IN
R
IN1
R
IN2
C
F
C
F1
R
F
V
BIAS
COMP
ERROR AMP
NCP81246
www.onsemi.com
17
Differential Current Feedback Amplifiers
Each phase of the two-phase rail has a low offset
differential amplifier to sense that phase current for current
balance and per phase OCP protection during soft-start.
The inputs to the CSNx and CSPx pins are high impedance
inputs. It is recommended that any external filter resistor
RCSN does not exceed 10 kW to avoid offset issues with
leakage current. It is also recommended that the voltage
sense element be no less than 0.5 mW for accurate current
balance. Fine tuning of this time constant is generally not
required. The individual phase current is summed into the
PWM comparator feedback this way current is balanced via
a current mode control approach.
R
CSN
+
L
PHASE
C
CSN
@ DCR
(eq. 2)
Figure 8.
CCSNRCSN
DCR LPHASE
12
SWNx
VOUT
CSPx
CSNx
Two-Phase Rail Total Current Sense Amplifier
The NCP81246 uses a patented approach to sum the phase
currents into a single temperature compensated total current
signal. This signal is then used to generate the output voltage
droop, total current limit, and the output current monitoring
functions. The total current signal is floating with respect to
CSREF. The current signal is the difference between
CSCOMP and CSREF. The Rref(n) resistors sum the signals
from the output side of the inductors to create a low
impedance virtual ground. The amplifier actively filters and
gains up the voltage applied across the inductors to recover
the voltage drop across the inductor series resistance (DCR).
Rth is placed near an inductor to sense the temperature of the
inductor. This allows the filter time constant and gain to be
a function of the Rth NTC resistor and compensate for the
change in the DCR with temperature.
Figure 9.
−
+
R
REF1
C
REF
CSCOMP
CSN1
CSN2
SWN1
SWN2
CSREF
CSSUM
R
REF2
R
PH1
R
PH2
C
CS1
C
CS2
R
CS2
R
CS1
R
TH
10 W
10 W
1 nF
165 kW 75 kW
220 kW
The DC gain equation for the current sensing:
V
CSCOMP*CSREF
+*
R
CS2
)
R
CS1
@R
TH
R
CS1
)R
TH
R
PH
@
ǒ
I
OUT
Total
@ DCR
Ǔ
(eq. 3)
NCP81246
www.onsemi.com
18
Set the gain by adjusting the value of the R
PH
resistors.
The DC gain should be set to the output voltage droop. If the
voltage from CSCOMP to CSREF is less than 100 mV at
ICCMAX then it is recommend increasing the gain of the
CSCOMP amp. This is required to provide a good current
signal to offset voltage ratio for the ILIMIT pin. When no
droop is needed, the gain of the amplifier should be set to
provide ~100 mV across the current limit programming
resistor at full load. The NTC should be placed near the
closest inductor. The output voltage droop should be set with
the droop filter divider.
The pole frequency in the CSCOMP filter should be set
equal to the zero from the output inductor. This allows the
circuit to recover the inductor DCR voltage drop current
signal. C
CS1
and C
CS2
are in parallel to allow for fine tuning
of the time constant using commonly available values. It is
best to fine tune this filter during transient testing.
F
Z
+
DCR @ 25 C
2 @ p @ L
Phase
(eq. 4)
°
Two-Phase Rail Programming the Current Limit
The current limit thresholds are programmed with
a resistor between the ILIMIT and CSCOMP pins.
The ILIMIT pin mirrors the voltage at the CSREF pin and
mirrors the sink current internally to IOUT (reduced by the
IOUT Current Gain) and the current limit comparators.
The 100% current limit trips if the ILIMIT sink current
exceeds 10 mA for 50 ms. The 150% current limit trips with
minimal delay if the ILIMIT sink current exceeds 15 mA. Set
the value of the current limit resistor based on the
CSCOMP-CSREF voltage as shown below.
(eq. 5)
R
LIMIT
+
R
CS2
)
R
CS1
@R
TH
R
CS1
)R
TH
R
PH
@
ǒ
I
OUT
Total
@ DCR
Ǔ
10 m
or
(eq. 6)
R
LIMIT
+
V
CSCOMP*CSREF @ ILIMIT
10 m
Two-Phase Rail Programming DAC Feed-Forward
Filter
The DAC feed-forward implementation is realized by
having a filter on the VSN pin. Programming R
VSN
sets the
gain of the DAC feed-forward and C
VSN
provides the time
constant to cancel the time constant of the system per the
following equations. C
OUT
is the total output capacitance
and R
OUT
is the output impedance of the system.
Figure 10.
12
12
VSN
C67
510 pF
R68
2.1 kW
VSS_SENSE
R
VSN
+ C
OUT
@ R
OUT
@ 453.6 @ 10
6
(eq. 7)
(eq. 8)
C
VSN
+
R
OUT
@ C
OUT
R
VSN
Two-Phase Rail Programming DROOP
The signals CSCOMP and CSREF are differentially
summed with the output voltage feedback to add precision
voltage droop to the output voltage.
Figure 11.
−
+
CSCOMP
CSREF
CSSUM
5
6
7
DROOP
(eq. 9)
Droop + DCR @
R
CS
R
PH
Two-Phase Rail Programming IOUT
The IOUT pin sources a current in proportion to the
ILIMIT sink current. The voltage on the IOUT pin is
monitored by the internal A/D converter and should be
scaled with an external resistor to ground such that a load
equal to ICC_MAX generates a 2 V signal on I
OUT
.
A pull-up resistor from 5 V VCC can be used to offset the
I
OUT
signal positive if needed.
(eq. 10)
R
IOUT
+
2.0 V @ R
LIMIT
10 @
R
CS2
)
R
CS1
@R
TH
R
CS1
)R
TH
R
PH
@
ǒ
I
OUT
ICC_MAX
@ DCR
Ǔ
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NCP81246MNTXG

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Buy NCP81246MNTXG
Manufacturer:
ON Semiconductor
Description:
Switching Controllers INDUSTRIAL TEMPERATURE
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