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THCV220-B

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
THine Electronics, Inc.
Security E
THCV220_Rev.2.20_E
Copyright©2016 THine Electronics, Inc.
4/18
Pin Description
THCV220 pin description
Pin Name Pin # type Description
R9-R0
40,41,42,43,45,
46,18,20,9,11
O3 pixel data outputs
G9-G0
33,34,36,37,38,
39,16,17,7,8
O3 pixel data outputs
B9-B0
25,26,27,28,31,
32,13,15,4,6
O3 pixel data outputs
CONT1,2 12,3 O3 User defined data outputs. Active only in 32bit mode.
DE 21 O3 DE Output
VSYNC 22 O3 Vsync Output
HSYNC 23 O3 Hsync Output
CLKOUT
30 O3 Pixel clock output
RXN/P 57,58
CI High-speed CML signal input.
LOCKN
51 OD3
Lock detect output.
Must be connected to Tx LOCKN with a 10kΩ pull-up resistor.
HTPDN
50 OD3
Hot plug detect output.
Must be connected to Tx HTPDN with a 10kΩ pull-up resistor.
PDN 47 I3L
Power down input.
H: Normal operation L: Power down
TTLDRV 64 I3
TTL outputs drive strength select input.
H : Normal drive strength L : Weak drive strength
OE 1 I3
Output enable input.
H: All CMOS outputs enabled
L: All CMOS outputs disabled, except for LOCKN, HTPDN
COL 63 I3
Data width setting.
H : 24bit L : 32bit
LFSEL 49 I3
Frequency range setting.
H: Low frequency operation L: Normal Operation
RF 2 I3
Output clock triggering edge select input
H: Rising edge L: Falling edge
BET 62 I3
Field-BET entry.
H : Field BET Operation L : Normal Operation
BETOUT 61 O3
Field BET result output. Must be left OPEN when NOT used.
LATEN 60 I3
Latch select input under Field-BET operation
H : Latched result L : NOT Latched result
TEST1 48 - Test pin, must be “L” for normal operation.
TEST2 53 - Test pin, must be “L” for normal operation.
CAPOUT 54 -
Decoupling capacitor pins.
This pin should be connected to external decoupling capacitors.
Recommended Capacitance is 2.2uF
CAPINA 55 -
Reference Input for Analog circuit.Must be tied CAPOUT.
VCC
5,14,19,29,
35,44
PS
Digital Power supply Pins
AVCC
52
PS
Analog Power supply Pin
GND
10,24,56,59
PS
Ground Pins
EXPGND 65
PS
Exposed Pad Ground
*type symbol
I3=3.3v CMOS input, I3L=Low Speed 3.3v CMOS input, O3=3.3v CMOS output, OD3=3.3v Open drain output
CI=CML input, PS=Power Supply
THine Electronics, Inc.
Security E
THCV220_Rev.2.20_E
Copyright©2016 THine Electronics, Inc.
5/18
Functional Description
Functional Overview
With V-by-One
®
HS proprietary encoding scheme and CDR (Clock and Data Recovery) architecture,
THCV220 enable transmission of 8/10 bit RGB, 2bits of user-defined data (CONT), synchronizing signals
HSYNC, VSYNC, and DE by a pair cable with minimal external components.
THCV220 automatically extracts the clock from the incoming data streams and converts the serial data into
video data with DE being high or synchronizing data with DE being low, recognizing which type of serial data is
being sent by the transmitter. And it outputs the recovered data in the form of CMOS/TTL data.
THCV220 can operate for a wide range of a serial bit rate from 600Mbps to 3.75Gbps.
It does not need any external frequency reference, such as a crystal oscillator.
Internal Reference Output/Input Function (CAPOUT,CAPINA)
An internal regulator produces the 1.2V (CAPOUT). This 1.2V linear regulator can not supply any other
external loads. Bypass CAPOUT to GND with 2.2uF.
CAPINA supplies reference voltage for any internal analog circuit also. Bypass CAPINA to GND with 0.1uF
to remove high frequency noise. CAPOUT and CAPINA must be tied together.
Analog power supply AVCC is supposed to be stabilized with de-coupling capacitor and series noise filter (for
example, ferrite bead).
Figure 1. Connection of CAPOUT, CAPINA and Decoupling Capacitor
CAPOUT
CAPINA
THCV220
2.2uF
0.1uF
AVCC
Power
Supply
THine Electronics, Inc.
Security E
THCV220_Rev.2.20_E
Copyright©2016 THine Electronics, Inc.
6/18
Data Enable
Figure 2 is the conceptual diagram of the basic operation of the chipset. THCV219 in Figure 2 is an example of
V-by-One® HS Transmitter.
There are some requirements for DE. Figure 3 shows the timing diagram of it.
R/G/B
CONT
V,HSYNC
CTL
1
DE
THCV220THCV219
R/G/B
CONT
VSYNC
HSYNC
DE=1, R/G/B,CONT
DE=0, CTL
DE=1, V,HSYNC=Fixed
DE=0, V,HSYNC
0
CTL are particular assigned bit among R/G/B,CONT
that can carry arbitrary data during DE=0 period.
Figure 2. Conceptual diagram of the basic operation of the chipset
High Low High
Valid Data
Valid Data
Invalid
Invalid
DE
HSYNC
VSYNC
RGB
CONT
THCV219
Input*
Invalid
Valid Data
CLKIN
Low
Valid Data
Invalid Invalid
Valid Data
Low High
Invalid
Valid Data
(RF=H)
High Low High
Valid Data
Valid Data
Keep the last data
of DE=L period
DE
HSYNC
VSYNC
RGB
CONT
Valid Data
CLKOUT
Low
Valid Data
Valid Data
Low High
Valid Data
(RF=H)
Keep the last data
of DE=L period
Keep the last data
of DE=L period
Particular assigned bit ‘CTL’ is transmitted expect the first
and last pixel of Blanking period. Ohters are Low fixed.
t
DEH
t
DEL
t
DEH
t
DEL
Keep the
last data
Keep the
last data
Keep the
last data
*Refer to the data sheet of THCV219 for input operation
THCV220
Output
Figure 3. Data and synchronizing signals transmission timing diagram
Table 1. DE requirement
symbol Parameter min. typ. max. Unit
tDEH DE=High Duration 2tRCP sec
tDEL DE=Low Duration 2tRCP sec
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

THCV220-B

Mfr. #:
Buy THCV220-B
Manufacturer:
CEL
Description:
Serializers & Deserializers - Serdes HS Rx to CMOS Single V by One
Lifecycle:
New from this manufacturer.
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