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Color Depth and Frequency Range Select function
THCV220 support a variety of data width and frequency range. Refer to Table 2 for details.
Table 2. operation mode select
COL
LFSEL
Description
Freq. Range
L
L
32bit
15 to 93M
H
32bit Low frequency mode
7.5 to 30M
H
L
24bit
20 to 125M
H
24bit Low frequency mode
10 to 40M
Hot-Plug Function
HTPDN indicates connecting condition between the Transmitter and the Receiver. HTPDN of the transmitter
side is high when the Receiver is not active or not connected. Then Transmitter can enter into the power down
mode. HTPDN is set to Low by the Receiver when Receiver is active and connects to the Transmitter, and then
Transmitter must start up and transmit CDR training pattern for link training. HTPDN is open drain output at the
receiver side. Pull-up resistor is needed at the transmitter side.
HTPDN connection between the Transmitter and the Receiver can be omitted as an application option. In this
case, HTPDN at the Transmitter side should always be taken as Low.
Lock Detect Function
LOCKN indicates whether the CDR PLL is in the lock state or not. LOCKN at the Transmitter input is set to
High by pull-up resistor when Receiver is not active or at the CDR PLL training state. LOCKN is set to Low by
the Receiver when CDR lock is done. Then the CDR training mode finishes and Transmitter shifts to the normal
mode. LOCKN is open drain output at the receiver side. Pull-up resistor is needed at the transmitter side.
When HTPDN is included in an application, the LOCKN signal should only be considered when the HTPDN is
pulled low by the Receiver.
Vcc
(Tx side)
HTPDN
LOCKN
10kΩ
HTPDN
LOCKN
THCV220
10kΩ
Vcc
(Tx side)
HTPDN
LOCKN
HTPDN
LOCKN
THCV220
10kΩ
With HTPDN connect Without HTPDN connect
V-by-One®
HS Tx
V-by-One®
HS Tx
Figure 4. Hot-plug and Lock detect scheme
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Drive Select Function
TTLDRV pin controls TTL output strength. See Table 3.
Table 3. Drive Select function table
TTLDRV
Description
L
Weak TTL output strength
H
Normal TTL output strength
Power Down Function
Setting the PDN pin low places THCV220 in the power-down mode. Internal circuitry turns off and the CMOS
outputs drives low or Hi-Z depends on OE pin.
Table 4. Power Down function table
PDN
Description
L
Power Down
H
Normal Operation
Output Enable Function
OE pin select CMOS/TTL output states. It is enabled with OE=H. When OE=L, CMOS/TTL outputs turns
high-Z. See Table 5.
Table 5. OE function table
PDN
OE
CMOS/TTL Output
*
L
Hi-Z
L
H
Low Fixed
H
Normal Operation
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Field BET Operation
In order to help users to check validity of CML high-speed serial line, THCV220 has an operation mode in
which they act as a bit error tester (BET). THCV219 which is an example of Tx device also has BET function
mode. In this mode, THCV219 internally generates test pattern which is then serialized onto the CML
high-speed line. THCV220 receives the data stream and checks bit errors.
This "Field BET" mode is activated by setting BET= H both on THCV219 and THCV220. The generated data
pattern is then 8b/10b encoded, scrambled, and serialized onto the CML channel. As for THCV220, the internal
test pattern check circuit gets enabled and reports result on BETOUT pin. The BETOUT pin goes LOW
whenever bit errors occur, or it stays HIGH when there is no bit error. Please refer to Table 6. User can select
two kinds of check result, “Latched-result” or “NOT latched result”. The latch is reset by setting LATEN=L.
Table 6. Field BET operation pin settings
THCV219
THCV220
Condition
BET
BET
LATEN
Operation
Output Latch select
L
L
L
Normal Operation
-
H
Forbidden
-
H
H
L
Field BET Operation
NOT latched result
H
H
H
Latched result
Table 7. THCV220 Field BET result
BETOUT
Output
L
Bit error occurred
H
No error
THCV219 THCV220
CLKIN
BET=H BET=H
Test Pattern
Checker
Test Pattern
Generator
TTL data inputs
are ignored
BETOUT
Test Point
for
Field BET
LATEN
Figure 5. Field BET Configuration

THCV220-B

Mfr. #:
Manufacturer:
CEL
Description:
Serializers & Deserializers - Serdes HS Rx to CMOS Single V by One
Lifecycle:
New from this manufacturer.
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