LTC2442
5
2442fb
For more information www.linear.com/LTC2442
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: V
CC
= 4.5V to 5.5V unless otherwise specified.
V
REF
= REF
+
– REF
–
, V
REFCM
= (REF
+
+ REF
–
)/2;
V
IN
= SEL
+
– SEL
–
, V
INCM
= (SEL
+
+ SEL
–
)/2.
Note 4: F
O
pin tied to GND or to external conversion clock source with
f
EOSC
= 10MHz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: The converter uses the internal oscillator.
Note 8: The converter is in external SCK mode of operation such that the
SCK pin is used as a digital input. The frequency of the clock signal driving
SCK during the data output is f
ESCK
and is expressed in Hz.
Note 9: The converter is in internal SCK mode of operation such that the
SCK pin is used
as a digital output. In this mode of operation, the SCK pin
has a total equivalent load capacitance of C
LOAD
= 20pF.
Note 10: The external oscillator is connected to the F
O
pin. The external
oscillator frequency, f
EOSC
, is expressed in Hz.
Note 11: The converter uses the internal oscillator. F
O
= 0V.
Note 12: Guaranteed by design and test correlation.
Note 13: There is an internal reset that adds an additional 5 to 15 f
O
cycles
to the conversion time.
Note 14: In order to achieve optimum linearity, the amplifier power
positive supply input (V
+
) must exceed the maximum input voltage level by
2V or greater. The negative amplifier power supply input (V
–
) must be at
least 200mV below the minimum input voltage level.
Note 15: Amplifiers are externally compensated with 0.1µF.
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
EOSC
External Oscillator Frequency Range
l
0.1 12 MHz
t
HEO
External Oscillator High Period
l
25 10000 ns
t
LEO
External Oscillator Low Period
l
25 10000 ns
t
CONV
Conversion Time OSR = 256 (SDI = 0)
OSR = 32768 (SDI = 1)
External Oscillator, 1x Mode
(Notes 10, 13)
l
l
l
0.99
126
1.13
145
40 • OSR + 178
f
EOSC
(KHz)
1.33
170
ms
ms
ms
f
ISCK
Internal SCK Frequency Internal Oscillator (Note 9)
External Oscillator (Notes 9, 10)
l
0.8 0.9
f
EOSC
/10
1 MHz
Hz
D
ISCK
Internal SCK Duty Cycle (Note 9)
l
45 55 %
f
ESCK
External SCK Frequency Range (Note 8)
l
20 MHz
fLESCK External SCK Low Period (Note 8)
l
25 ns
t
HESCK
External SCK High Period (Note 8)
l
25 ns
t
DOUT_ISCK
Internal SCK 32-Bit Data Output Time Internal Oscillator (Notes 9, 11)
External Oscillator (Notes 9, 10)
l
l
30.9 35.3
320/f
EOSC
41.6 µs
s
t
DOUT_ESCK
External SCK 32-Bit Data Output Time (Note 8)
l
32/f
ESCK
s
t
1
CS ↓ to SDO Low Z
(Note 12)
l
0 25 ns
t
2
CS ↑ to SDO High Z
(Note 12)
l
0 25 ns
t
3
CS ↓ to SCK ↓
(Note 9) 5 µs
t
4
CS ↓ to SCK ↑
(Note 8, 12)
l
25 ns
t
KQMAX
SCK ↓ to SDO Valid
l
25 ns
t
KQMIN
SDO Hold After SCK ↓
(Note 5)
l
15 ns
t
5
SCK Setup Before CS ↓
l
50 ns
t
6
SCK Hold After CS ↓
l
50 ns
t
7
SDI Setup Before SCK ↑
(Note 5)
l
10 ns
t
8
SDI Hold After SCK ↑
(Note 5)
l
10 ns
TIMING CHARACTERISTICS
