pdf: 09005aef81a2f214/source: 09005aef81a2f22d Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF18C64_128_256x72F.fm - Rev. B 9/07 EN
4 ©2005 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM
Pin Assignments and Descriptions
Table 6: Pin Descriptions
Symbol Type Description
PS0–PS9 Input
Primary southbound data, positive lines.
PS0#–PS9# Input
Primary southbound data, negative lines.
SCL Input
Serial presence-detect (SPD) clock input.
SCK Input
System clock input, positive line.
SCK# Input
System clock Input, negative line.
SS0–SS9 Input
Secondary southbound data, positive lines.
SS0#–SS9# Input
Secondary southbound data, negative lines.
PN0–PN13 Output
Primary northbound data, positive lines.
PN0#–PN13# Output
Primary northbound data, negative lines.
SN0–SN13 Output
Secondary northbound data, positive lines.
SN0#–SN13# Output
Secondary northbound data, negative lines.
SA0–SA2 I/O
SPD address inputs; also used to select the FBDIMM number in the AMB.
SDA I/O
SPD data input/output.
RESET# Supply
AMB reset signal.
V
CC Supply
AMB core power and AMB channel interface power (1.5V).
V
DD Supply
DRAM power and AMB DRAM I/O power (1.8V).
V
DDSPD Supply
SPD/AMB SMBus power (3.3V).
V
SS Supply
Ground.
V
TT Supply
DRAM address/command/clock termination power (VDD/2).
M_TEST –
The M_TEST pin provides an external connection for testing the margin of V
REF, which is
produced by a voltage divider on the module. It is not intended to be used in normal system
operation and must not be connected (DNU) in a system. This test pin may have other
features on future card designs and will be included in this specification at that time.
DNU –
Do not use.
NC –
No connect: These pins are not connected on the module.
