MT18HTF25672FY-53EA5D3 Datasheet MT18HTF12872FY-53EB5D3, MT18HTF12872FY-53EB5E3, MT18HTF12872FY-53ED5E3 | P7-P9

pdf: 09005aef81a2f214/source: 09005aef81a2f22d Micron Technology, Inc., reserves the right to change products or specifications without notice.

HTF18C64_128_256x72F.fm - Rev. B 9/07 EN

1GB, 2GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM

General Description

The Micron FBDIMM adheres to the currently proposed industry specifications for

FBDIMMs. The following specifications contain detailed information on FBDIMM

design, interfaces, and theory of operation, and are listed here for the system designers’

convenience. Refer to the JEDEC Web site for available specifications.

• FBDIMM Design Specification – pending JEDEC approval

• FBDIMM: Architecture and Protocol – JESD206

• FBDIMM: Advanced Memory Buffer (AMB) – JESD82-20

• Design for Test, Design for Validation (DFx) Specification

• Serial Presence-Detect (SPD) for Fully Buffered DIMM – JEDEC Standard No. 21-C

page 4.1.2.7-1

The MT18HTF12872F and MT18HTF25672F DDR2 SDRAM modules are a high-band-

width, large-capacity channel solution that have a narrow host interface. FBDIMMs use

DDR2 SDRAM devices isolated from the channel behind an AMB buffer on the

FBDIMM. Memory device capacity remains high, and total memory capacity scales with

DDR2 SDRAM bit density.

As shown in Figure 2 on page 5, the FBDIMM channel provides a communication path

from a host controller to an array of DDR2 SDRAM devices, with the DDR2 SDRAM

devices buffered behind an AMB device. The physical isolation of the DDR2 SDRAM

devices from the channel enhances the communication path and significantly increases

the reliability and availability of the memory subsystem.

Advanced Memory Buffer

The AMB isolates the DDR2 SDRAM devices from the channel. This single-chip AMB

component, located in the center of each FBDIMM, acts as a repeater and buffer for all

signals and commands exchanged between the host controller and DDR2 SDRAM

devices, including data input and output. The AMB communicates with the host

controller and adjacent FBDIMMs on a system board using an industry-standard, high-

speed, differential, 1.5V, point-to-point interface. The AMB also enables buffering of

memory traffic to support large memory capacities. Refer to the JEDEC JESD82-20 spec-

ification for further information.

pdf: 09005aef81a2f214/source: 09005aef81a2f22d Micron Technology, Inc., reserves the right to change products or specifications without notice.

HTF18C64_128_256x72F.fm - Rev. B 9/07 EN

1GB, 2GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM

Electrical Specifications

Stresses greater than those listed in Table 7 may cause permanent damage to the

module. This is a stress rating only, and functional operation of the module at these or

any other conditions outside those indicated in the device data sheet is not implied.

Exposure to absolute maximum rating conditions for extended periods may adversely

affect reliability.

Notes: 1. VIN should not be greater than VCC.

2. T

is specified at 95°C only when using 2X refresh timing (

REFI = 7.8µs at or below 85°C;

REFI = 3.9µs above 85°C); refer to the DDR2 SDRAM component data sheet.

3. See applicable DDR2 SDRAM component data sheet for

REFI and extended mode register

settings. The

REFI parameter is used to specify the doubled refresh interval necessary to

sustain <85°C operation.

Notes: 1. Applies to AMB and SPD.

2. Applies to SMB and SPD bus signals.

3. Applies to AMB CMOS signal RESET#.

4. For all other AMB-related DC parameters, please refer to the high-speed differential link

interface specification.

Table 7: Absolute Maximum Ratings

Parameter Symbol Min Max Units Notes

Voltage on any pin relative to V

VIN, VOUT –0.3 +1.75 V 1

Voltage on V

CC pin relative to VSS

VCC –0.3 +1.75 V

Voltage on V

DD pin relative to VSS

VDD –0.5 +2.3 V

Voltage on V

TT pin relative to VSS

VTT –0.5 +2.3 V

DDR2 SDRAM device operating case temperature

0 +95 °C 2, 3

AMB device operating case temperature

0 +110 °C

Table 8: Input DC Voltage and Operating Conditions

Parameter Symbol Min Nom Max Units Notes

AMB supply voltage

CC 1.46 1.5 1.54 V

DDR2 SDRAM supply voltage

DD 1.7 1.8 1.9 V

Termination voltage

TT 0.48 × VDD 0.5 × VDD 0.52 × VDD V

EEPROM supply voltage

DDSPD 3.0 3.3 3.6 V 1

SPD input high (logic 1) voltage

IH(DC)2.1 –VDDSPD V2

SPD input low (logic 0) voltage

IL(DC)– – 0.8V2

RESET input high (logic 1) voltage

IH(DC)1.0 – – V3

RESET input low (logic 0) voltage

IL(DC)– – 0.5V2

Leakage current (RESET)

L –90 – +90 µA 3

Leakage current (link)

L –5.0 – +5.0 µA 4

Table 9: Clock Rates

FBDIMM Link

Data Rate Reference Clock DRAM Clock

DRAM

Data Rate

3.2 Gb/s 133 MHz 266 MHz 533 Mb/s

4.0 Gb/s 167 MHz 333 MHz 666 Mb/s

4.8 Gb/s 200 MHz 400 MHz 800 Mb/s

pdf: 09005aef81a2f214/source: 09005aef81a2f22d Micron Technology, Inc., reserves the right to change products or specifications without notice.

HTF18C64_128_256x72F.fm - Rev. B 9/07 EN

1GB, 2GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM

Conditions and Specifications

IDD Conditions and Specifications

Notes: 1. Actual test conditions may vary from published JEDEC test conditions.

Notes: 1. Total power is based on maximum voltage levels, I

CC @ 1.575V and IDD @ 1.9V.

Table 10: IDD Conditions

Symbol Condition

DD_Idle_0 Idle current, single, or last DIMM: L0 state; Idle (0 percent bandwidth); Primary channel

enabled; Secondary channel disabled; CKE HIGH; Command and address lines stable; DDR2

SDRAM clock active

DD_Idle_1 Idle current, first DIMM: L0 state; Idle (0 percent bandwidth); Primary and secondary

channels enabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active

DD_Active_1 Active power: L0 state; 50 percent DRAM bandwidth; 67 percent READ; 33 percent WRITE;

Primary and secondary channels enabled; DDR2 SDRAM clock active; CKE HIGH

DD_Active_2 Active power, data pass through: L0 state; 50 percent DRAM bandwidth to downstream

DIMM; 67 percent READ; 33 percent WRITE; Primary and secondary channels enabled; DDR2

SDRAM clock active; CKE HIGH; Command and address lines stable

DD_Training Training: Primary and secondary channels enabled; 100 percent toggle on all channel lanes;

DRAMs idle; 0 percent bandwidth; CKE HIGH; Command and address lines stable; DDR2

SDRAM clock active

DD_IBIST IBIST over all IBIST modes: DRAM idle (0 percent bandwidth); Primary channel enabled;

Secondary channel enabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM

clock active

DD_EI Electrical idle: DRAM idle (0 percent bandwidth); Primary channel disabled; Secondary

channel disabled; CKE LOW; Command and address lines floated; DDR2 SDRAM clock active;

ODT and CKE driven LOW

Table 11: IDD Specifications – 1GB DDR2-533

Symbol IDD_Idle_0 IDD_Idle_1 IDD_Active_1 IDD_Active_2 IDD_Training IDD_IBIST IDD_EI Units

2,200 3,000 3,400 3,200 3,500 3,800 2,000 mA

1,620 1,620 3,470 1,620 1,620 1,620 326 mA

Total power

6.5 7.8 11.9 8.1 8.6 9.0 3.8 W

Table 12: IDD Specifications – 1GB DDR2-667

Symbol IDD_Idle_0 IDD_Idle_1 IDD_Active_1 IDD_Active_2 IDD_Training IDD_IBIST IDD_EI Units

2,600 3,400 3,900 3,700 4,000 4,500 2,500 mA

1,710 1,710 3,845 1,710 1,710 1,710 326 mA

Total power

7.3 8.6 13.4 9.0 9.5 10.3 4.6 W

Table 13: IDD Specifications – 1GB DDR2-800

Symbol IDD_Idle_0 IDD_Idle_1 IDD_Active_1 IDD_Active_2 IDD_Training IDD_IBIST IDD_EI Units

TBD TBD TBD TBD TBD TBD TBD mA

Total power

TBD TBD TBD TBD TBD TBD TBD W

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

MT18HTF25672FY-53EA5D3

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Manufacturer:

Micron

Description:

MODULE DDR2 SDRAM 2GB 240FBDIMM

Lifecycle:

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MT18HTF25672FY-53EA5D3

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