1 of 36 092302
DS1961S
1kb Protected EEPROM iButton
With SHA-1 Engine
www.maxim-ic.com
SPECIAL FEATURES
§ 1128 Bits of 5V EEPROM Memory
Partitioned into Four Pages of 256 Bits, a 64-
Bit Write-Only Secret, and up to Five
General-Purpose Read/Write Registers
§ Write Access Requires Knowledge of the
Secret and the Capability of Computing and
Transmitting a 160-Bit MAC (Message
Authentication Code) as Authorization
§ Secret and Data Memory can be Write-
Protected (All or Page 0 Only) or put in
EPROM-Emulation Mode (“Write to 0”, Page
1)
§ On-Chip, 512-Bit SHA-1 Engine to Compute
160-Bit MACs and Generate Secrets
§ Reads and Writes Over a Wide 2.8V to 5.25V
Voltage Range from -40°C to +85°C
§ Communicates to Host with a Single Digital
Signal at 14.1kbps using 1-Wire
®
Protocol
§ On-Chip, 16-Bit Cyclic Redundancy Check
(CRC) Generator for Safeguarding Data
Transfers
§ Overdrive Mode Boosts Communication
Speed to 125kbps
§ Operating Temperature Range from -40°C to
+85°C
§ Minimum 10 Years of Data Retention at
+85°C
COMMON iButton FEATURES
§ Unique, Factory-Lasered and Tested 64-Bit
Registration Number (8-Bit Family Code +
48-Bit Serial Number + 8-Bit CRC Tester)
Assures Absolute Traceability Because No
Two Parts are Alike
§ Multidrop Controller for 1-Wire Net
§ Digital Identification and Information by
Momentary Contact
§ Chip-Based Data Carrier Compactly Stores
Information
§ Data can be Accessed While Affixed to
Object
§ Button Shape is Self-Aligning with Cup-
Shaped Probes
§ Durable Stainless-Steel Case Engraved with
Registration Number Withstands Harsh
Environments
§ Easily Affixed with Self-Stick Adhesive
Backing, Latched by its Flange, or Locked
with a Ring Pressed onto its Rim
§ Presence Detector Acknowledges when
Reader First Applies Voltage
§ Meets UL#913 (4th Edit.). Intrinsically Safe
Apparatus: Approved Under Entity Concept
for use in Class I, Division 1, Groups A, B, C,
and D Locations (Application Pending)
F5 MicroCan
IO
GND
0.36
0.51
5.89
© 1993
YYWW REGISTERED RR
xx
33
000000FBD8B3
16.25
17.35
F3 MicroCan
IO
GND
0.36
© 1993
YYWW REGISTERED RR
xx
33
000000FBC52B
16.25
17.35
0.51
3.10
All dimensions are shown in millimeters.
iButton, 1-Wire, and MicroCan are registered trademarks of
Dallas Semiconductor.
DS1961S
2 of 36
ORDERING INFORMATION
DS1961S-F5 F5 iButton
DS1961S-F3 F3 iButton
EXAMPLES OF ACCESSORIES
DS1963S SHA Coprocessor and Button
DS9096P Self-Stick Adhesive Pad
DS9101 Multipurpose Clip
DS9093RA Mounting Lock Ring
DS9093A Snap-In Fob
DS9092 iButton Probe
iButton DESCRIPTION
The DS1961S combines 1024 bits of EEPROM, a 64-bit secret, an 8-byte register/control page with up to
five user-read/write bytes, a 512-bit SHA-1 engine, and a fully featured 1-Wire interface in a rugged
iButton. Data is transferred serially through the 1-Wire protocol, which requires only a single data lead
and a ground return. The DS1961S has an additional memory area called the scratchpad that acts as a
buffer when writing to the main memory, the register page, or when installing a new secret. Data is first
written to the scratchpad from where it can be read back. After the data has been verified, a copy
scratchpad command transfers the data to its final memory location, provided that the DS1961S receives
a matching 160-bit MAC. The computation of the MAC involves the secret and additional data stored in
the DS1961S including the device’s identity register. Only a new secret can be loaded without providing
a MAC. The SHA-1 engine can also be activated to compute 160-bit MACs when reading a memory page
or to compute a new secret, instead of loading it.
The DS1961S understands a unique command "Refresh Scratchpad." Proper use of a refresh sequence
after a copy scratchpad operation reduces the number of weak bit failures in a touch environment (see the
Writing with Verification section). The refresh sequence also provides a means to restore functionality in
a device with bits in a weak state.
Each DS1961S has its own 64-bit ROM registration number that is factory lasered into the chip to
provide a guaranteed unique identity for absolute traceability. The durable stainless-steel package is
highly resistant to environmental hazards such as dirt, moisture, and shock. Its compact coin-shaped
profile is self-aligning with mating receptacles, allowing the DS1961S to be easily used by human
operators. Accessories permit the DS1961S to be mounted on almost any surface including plastic key
fobs and photo-ID badges.
APPLICATIONS
The DS1961S can be used for different purposes such as secure access control, user/product authentica-
tion, after-market management of consumables, and as monetary tokens in electronic payment systems.
As carrier of electronic cash (eCash), the DS1961S can store up to three monetary files or "purses" of a
single service provider, which make the device well suited for company-sized single-secret applications
such as cafeteria, copy machines, and access control at entertainment parks or private clubs. For increased
security or if the processing power of the host microcontroller is insufficient, a DS1963S can be used as
secure coprocessor to verify MACs generated by the DS1961S or to compute MACs needed for writing
to the DS1961S.
OVERVIEW
The block diagram in Figure 1 shows the relationships between the major control and memory sections of
the DS1961S. The DS1961S has five main data components: 1) 64-bit lasered ROM, 2) 64-bit scratchpad,
3) four 32-byte pages of EEPROM, 4) 64-bit register page, 5) 64-bit secrets memory, and 6) a 512-bit
DS1961S
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SHA-1 (Secure Hash Algorithm) engine. The hierarchical structure of the 1-Wire protocol is shown in
Figure 2. The bus master must first provide one of the seven ROM function commands, 1) Read ROM, 2)
Match ROM, 3) Search ROM, 4) Skip ROM, 5) Resume Communication, 6) Overdrive-Skip ROM, or 7)
Overdrive-Match ROM. Upon completion of an overdrive ROM command byte executed at standard
speed, the device enters overdrive mode where all subsequent communication occurs at a higher speed.
The protocol required for these ROM function commands is described in Figure 9. After a ROM function
command is successfully executed, the memory functions become accessible and the master can provide
any one of the eight memory and SHA function commands. The protocol for these memory and SHA
function commands is described in Figure 7. All data is read and written LSB first.
Figure 1. DS1961S BLOCK DIAGRAM
Parasite Power
1-Wire Net
64-bit
Lasered ROM
1-Wire
Function Control
Secrets Memory
64-bit
64-bit
Scratchpad
Data Memory
4 Pages of
256 bits Each
CRC16
Generator
Memory and
SHA Function
Control Unit
512-bit
Secure Hash
Algorithm
Engine
Register Page
64-bit
64-BIT LASERED ROM
Each DS1961S contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire family
code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits (see
Figure 3). The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and
XOR gates as shown in Figure 4. The polynomial is X
8
+ X
5
+ X
4
+ 1. Additional information about the
Dallas 1-Wire CRC is available in The Book of DS19xx iButton Standards from Dallas Semiconductor.
The shift register bits are initialized to zero. Then starting with the LSB of the family code, one bit at a
time is shifted in. After the 8th bit of the family code has been entered, then the serial number is entered.
After the 48th bit of the serial number has been entered, the shift register contains the CRC value.
Shifting in the eight bits of CRC should return the shift register to all zeros.

DS1961S-F5+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
iButtons & Accessories 1kb Protected EEPROM iButton w/SHA-1 Eng
Lifecycle:
New from this manufacturer.
Delivery:
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