DS1961S
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Read-/Write-Time Slots
Data communication with the DS1961S takes place in time slots that carry a single bit each. Write-time
slots transport data from bus master to slave. Read-time slots transfer data from slave to master. The
definitions of the write- and read-time slots are illustrated in Figure 11.
All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line
falls below the threshold V
TL
, the DS1961S starts its internal time base. The tolerance of the slave time
base creates a slave-sampling window that stretches from t
SLSMIN
to t
SLSMAX
. The voltage on the data line
at the sampling point determines whether the DS1961S decodes the time slot as 1 or 0. For reliable
communication the voltage has to be either below the V
ILMAX
or above the maximum V
TH
value during
the entire sampling window.
Master-to-Slave
For a write-one time slot, the master pulldown time (t
MPD1
= t
W1L
-e + t
F
) must be short enough to allow
the voltage on the 1-Wire line to reach V
TH
at t
SLSMIN
, the earliest sampling point of a DS1961S. After the
latest sampling point (t
SLSMAX
) there needs to be a recovery time (t
REC
) before the next time slot can start.
For a write-zero time slot, the master pulldown time (t
MPD0
= t
W0L
+ t
F
) must be long enough to keep the
voltage on the data line below V
ILMAX
at the sampling point of a slow DS1961S, which is t
SLSMAX
. Before
the next time slot can start, the voltage on the data line first needs to rise above V
TH
and remain there
until the recovery time t
REC
is expired.
Slave-to-Master
A read-data time slot is very similar to a write-one time slot. The master begins a read-data time slot with
pulling the data line low. As the voltage on the 1-Wire line falls below the threshold V
TL
, the DS1961S
starts its internal time base. The master pulldown time (t
MPDR
= t
RL
+ t
F
) must be long enough to cover the
setup time t
SU
, after which the DS1961S delivers a bit to its 1-Wire port. When transmitting a 0, the
DS1961S holds the data line low for t
SPD
. If the data bit is a 1, the DS1961S does not hold the data line
low at all.
The master samples the data line at t
MSR
, inside a window that is determined by the sum of t
RL
and the rise
time (d) on one side and t
SPDMIN
on the other side. The optimum sample point for a read-zero case is no
later than t
SPDMIN
. In case of a read-one, the voltage on the 1-Wire line must be able to reach V
IHMASTER
at
t
MSR
. This condition determines the maximum duration of the master pulldown time. For reliable
communication, the master pulldown time should be as short as possible, maximizing the time for the
data line to reach V
IHMIN
. Before the next time slot can start, t
SPDMAX
needs to be over and the voltage on
the data line must have risen above V
TH
and remained there until the recovery time t
REC
is expired.
