DS1961S
25 of 36
The master can read the MAC with the read authenticated page command in a register and bit sequence as
shown in Table 3. With the copy scratchpad command the bit transmission sequence is the same,
however, the master has to compute the MAC and send it to the DS1961S. With the compute next secret
command the MAC is not exposed. Instead, the contents of the D and E SHA computation registers are
directly copied to the secret, as shown in Table 1.
1-WIRE BUS SYSTEM
The 1-Wire bus is a system, which has a single bus master and one or more slaves. In all instances the
DS1961S is a slave device. The bus master is typically a microcontroller. For small configurations the 1-
Wire communication signals can be generated under software control using a single port pin. For larger
configurations, the DS2480B 1-Wire line driver chip or serial port adapters based on this chip (DS9097U
series) are recommended. This simplifies the hardware design and frees the microprocessor from
responding in real-time.
The discussion of this bus system is broken down into three topics: hardware configuration, transaction
sequence, and 1-Wire signaling (signal types and timing). The 1-Wire protocol defines bus transactions in
terms of the bus state during specific time slots that are initiated on the falling edge of sync pulses from
the bus master. For a more detailed protocol description, refer to Chapter 4 of The Book of DS19xx
iButton Standards.
HARDWARE CONFIGURATION
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to
drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open-
drain or tri-state outputs. The 1-Wire port of the DS1961S is open drain with an internal circuit equivalent
to that shown in Figure 8.
A multidrop bus consists of a 1-Wire bus with multiple slaves attached. At standard speed the 1-Wire bus
has a maximum data rate of 16.3kbps. The speed can be boosted to 142kbps by activating the overdrive
mode. The DS1961S is not guaranteed to be fully compliant to the iButton standard. Its maximum data
rate in standard speed mode is 14.1kbps and 125kbps in overdrive. The DS1961S requires a 1-Wire
pullup resistor of maximum 2.2kW for executing any of its memory and SHA function commands at any
speed. When communicating with several DS1961S simultaneously, e.g., to install the same secret in
several devices, the resistor should be bypassed by a low-impedance pullup to V
PUP
while the device
transfers data from the scratchpad to the EEPROM.
The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus
must be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low
for more than 16µs (overdrive speed) or more than 120µs (regular speed), one or more devices on the bus
can be reset. With the DS1961S the bus must be left low for no longer than 15.2µs at overdrive speed to
ensure that none of the slave devices on the 1-Wire bus performs a reset. Despite of its limited
compliance, the DS1961S communicates properly when used in conjunction with a DS2480B 1-Wire
driver and serial port adapters that are based on this driver chip.
