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HVF18C64_128_256x72G.fm - Rev. B 5/06 EN
4 ©2003 Micron Technology, Inc. All rights reserved.
1GB (x72, ECC, SR) 240-Pin DDR2 VLP RDIMM
Pin Assignments and Descriptions
Table 5: Pin Descriptions
Refer to Table 4 on page 3 for more information
Symbol Type Source Description
ODT0 Input
(SSTL18)
Register
On-die termination: ODT (registered HIGH) enables termination resistance
internal to the DDR2 SDRAM. When enabled, ODT is only applied to the
following pins: DQ, DQS, DQS#, and CB. The ODT input will be ignored if
disabled via the LOAD MODE command.
CK0, CK0# Input
(SSTL18)
PLL
Clock: CK and CK# are differential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge of CK and negative
edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the crossings
of CK and CK#.
CKE0 Input
(SSTL18)
Register
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW)
deactivates clocking circuitry on the DDR2 SDRAM..
S0# Input
(SSTL18)
Register
Chip select: S# enables (registered LOW) and disables (registered HIGH) the
command decoder.
RAS#, CAS#,
WE#
Input
(SSTL18)
Register
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command
being entered.
BA0, BA1 Input
(SSTL18)
Register
Bank address inputs: BA0–BA1/BA2 define to which device bank an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied. BA0–BA1/BA2 define
which mode register, including MR, EMR, EMR(2), and EMR(3), is loaded during
the LOAD MODE command.
A0–A13 Input
(SSTL18)
Register
Address inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE commands, to
select one location out of the memory array in the respective bank. A10
sampled during a PRECHARGE command determines whether the PRECHARGE
applies to one device bank (A10 LOW, device bank selected by BA0–BA1/BA2)
or all device banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command.
P
AR_IN Input
(SSTL18)
Register
Parity bit for the address and control bus.
SCL Input SPD
Serial clock for presence-detect: SCL is used to synchronize the presence-
detect data transfer to and from the module.
SA0–SA2 Input SPD
Presence-detect address inputs: These pins are used to configure the
presence-detect device.
RESET# Input
(LVCMOS)
Register
Asynchronously forces all registered outputs LOW when RESET# is LOW. This
signal can be used during power up to ensure that CKE is LOW and DQs are
High-Z.
DQS0–DQS17,
DQS0#–DQS17#
I/O
(SSTL18)
DRAM
Data strobe: Output with read data, input with write data for source
synchronous operation. Edge-aligned with read data, center-aligned with
write data. DQS# is only used when differential data strobe mode is enabled
via the LOAD MODE command.
DQ0–DQ63 I/O
(SSTL18)
DRAM
Data input/output: Bidirectional data bus.
CB0–CB7 I/O
(SSTL18)
DRAM
Check bits.
SDA I/O SPD
Serial presence-detect data: SDA is a bidirectional pin used to transfer
addresses and data into and out of the presence-detect portion of the module.
E
RR_OUT Output
(open drain)
Register
Parity error found on the address and control bus.
V
DD Supply DRAM,
PLL,
Register
Power supply: 1.8V ±0.1V.
V
DDQ Supply DRAM
DQ power supply: 1.8V ±0.1V.
