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MT18HVF12872Y-53EB1

P1-P3P4-P6P7-P9P10-P12P13-P15
PDF: 09005aef82255aba/Source: 09005aef82255a83 Micron Technology, Inc., reserves the right to change products or specifications without notice.
HVF18C64_128_256x72G.fm - Rev. B 5/06 EN
7 ©2003 Micron Technology, Inc. All rights reserved.
1GB (x72, ECC, SR) 240-Pin DDR2 VLP RDIMM
General Description
General Description
Refer to the DDR2 component data sheets for complete functionality. For the 1GB
RDIMM device, refer to the 512Mb (128 Meg x 4) component data sheet.
DDR2 SDRAM modules are high-speed, CMOS, dynamic random-access 1GB memory
modules organized in x72 configuration. DRAM specifications require the refresh rate to
double when T
CASE
exceeds 85°C. This also includes the use of the high-temperature
refresh option.
DDR2 SDRAM modules use double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 4n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bit-
wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding
n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM
device during READs and by the memory controller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data for WRITEs.
DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
PLL and Register Operation
DDR2 SDRAM modules operate in registered mode, where the command/address input
signals are latched in the registers on the rising clock edge and sent to the DDR2 SDRAM
devices on the following rising clock edge (data access is delayed by one clock cycle). A
phase-lock loop (PLL) on the module receives and redrives the differential clock signals
(CK, CK#) to the DDR2 SDRAM devices. The registers and PLL minimize system and
clock loading. PLL clock timing is defined by JEDEC specifications and ensured by use of
the JEDEC clock reference board. Registered mode will add one clock cycle to CL.
Serial Presence-Detect Operation
DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is
implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256
bytes. The first 128 bytes can be programmed by Micron to identify the module type and
various SDRAM organizations and timing parameters. The remaining 128 bytes of
storage are available for use by the customer. System READ/WRITE operations between
the master (system logic) and the slave EEPROM device occur via a standard I
2
C bus
using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which
provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on
the module, permanently disabling hardware write protect.
PDF: 09005aef82255aba/Source: 09005aef82255a83 Micron Technology, Inc., reserves the right to change products or specifications without notice.
HVF18C64_128_256x72G.fm - Rev. B 5/06 EN
8 ©2003 Micron Technology, Inc. All rights reserved.
1GB (x72, ECC, SR) 240-Pin DDR2 VLP RDIMM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed in Table 6 may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Capacitance
At DDR2 data rates, Micron encourages designers to simulate the performance of the
module to achieve optimum values. When inductance and delay parameters associated
with trace lengths are used in simulations, they are significantly more accurate and real-
istic than a gross estimation of module capacitance. Simulations can then render a
considerably more accurate result. JEDEC modules are now designed by using simula-
tions to close timing budgets.
Table 6: Absolute Maximum DC Ratings
Parameter Symbol Min Max Units
V
DD supply voltage relative to VSS
VDD –1.0 2.3 V
V
DDQ supply voltage relative to VSS
VDDQ–0.52.3 V
V
DDL supply voltage relative to Vss
VDDL–0.52.3 V
Voltage on any pin relative to V
SS
VIN, VOUT –0.5 2.3 V
Storage temperature (2X refresh at 95°C)
T
STG
–55 100 °C
DDR2 SDRAM device operating temperature
T
CASE
095°C
Input leakage current; Any input 0V ≤ V
IN ≤ VDD;
V
REF input 0V ≤ VIN ≤ 0.95V; all other pins not
under test = 0V
Command/address,
RAS#, CAS#, WE# S#,
CKE, CK, CK#, DM
I
I –10 10 µA
Output leakage current; 0V ≤ V
OUT ≤ VDDQ; DQs
and ODT are disabled
DQ, DQS, DQS# Ioz –10 10 µA
V
REF leakage current; VREF = valid VREF level
IVREF –46 46 µA
Table 7: DRAM Interface for DRAM I/O
DRAM (at each individual device pin)
Parameter Symbol Min Max Units
Input high (logic 1) voltage
V
IH(DC) VREF(DC) + 125 VDDQ + 300 mV
Input low (logic 0) voltage
V
IL(DC) –300 VREF(DC) - 125 mV
Input high (logic 1) voltage (-667 speed grade)
V
IH(AC) VREF(DC) + 200 – mV
Input low(logic 0) voltage (-667 speed grade)
V
IL(AC) – VREF(DC) - 200 mV
Input leakage current; any input 0V ≤ V
IN ≤ VDD; all other pins
not under test = 0V
Ii –10 10 uA
Output leakage current; 0V ≤ V
OUT ≤ VDDQ; DQ and ODT
disabled
Ioz –10 10 uA
Input/output capacitance
C
IO 5.5 10.5 pF
PDF: 09005aef82255aba/Source: 09005aef82255a83 Micron Technology, Inc., reserves the right to change products or specifications without notice.
HVF18C64_128_256x72G.fm - Rev. B 5/06 EN
9 ©2003 Micron Technology, Inc. All rights reserved.
1GB (x72, ECC, SR) 240-Pin DDR2 VLP RDIMM
I
DD
Specifications
IDD Specifications
Notes: 1. a = Value calculated as one module rank in this operating condition, and all other module
ranks in I
DD2P (CKE LOW) mode.
2. b = Value calculated reflects all module ranks in this operating condition.
Tabl e 8: DD R2 IDD Specifications and Conditions – 1GB
Values shown for MT47H128M4 DDR2 SDRAM only and are computed from values specified in the 512Mb
(128 Meg x 4) component data sheet
Parameter/Condition Symbol -667 -53E -40E Units
Operating one bank active-precharge current;
t
CK =
t
CK (IDD),
t
RC =
t
RC
(IDD),
t
RAS =
t
RAS MIN (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
IDD0
a
1,620 1,440 1,440 mA
Operating one bank active-read-precharge current; I
OUT = 0mA; BL = 4,
CL = CL (IDD), AL = 0;
t
CK =
t
CK (IDD),
t
RC =
t
RC (IDD),
t
RAS =
t
RAS MIN (IDD),
t
RCD =
t
RCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data pattern is same as I
DD4W
I
DD1
a
1,890 1,710 1,620 mA
Precharge power-down current; All device banks idle;
t
CK =
t
CK (IDD); CKE
is LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
I
DD2P
b
126 126 126 mA
Precharge quiet standby current; All device banks idle;
t
CK =
t
CK (IDD);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data
bus inputs are floating
IDD2Q
b
810 720 630 mA
Precharge standby current; All device banks idle;
t
CK =
t
CK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
IDD2N
b
900 810 720 mA
Active power-down current; All device banks open;
t
CK =
t
CK (IDD); CKE is LOW; Other control and address bus
inputs are stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
I
DD3P
b
630 540 450 mA
Slow PDN exit
MR[12] = 1
216 216 216 mA
Active standby current; All device banks open;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS
MAX (I
DD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Other control and address bus inputs are switching; Data bus inputs are
switching
I
DD3N
b
1,170 990 810 mA
Operating burst write current; All device banks open, Continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS MAX (IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switching
I
DD4W
a
3,060 2,520 2,070 mA
Operating burst read current; All device banks open, Continuous burst
reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS
MAX (I
DD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
I
DD4R
a
3,240 2,610 2,070 mA
Burst refresh current;
t
CK =
t
CK (IDD); REFRESH command at every
t
RFC (IDD)
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
I
DD5
b
3,240 3,060 2,970 mA
Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
I
DD6
b
126 126 126 mA
Operating bank interleave read current; All device banks interleaving
reads, I
OUT= 0mA; BL = 4, CL = CL (IDD), AL =
t
RCD (IDD) -1 ×
t
CK (IDD);
t
CK =
t
CK
(IDD),
t
RC =
t
RC (IDD),
t
RRD =
t
RRD (IDD),
t
RCD =
t
RCD (IDD); CKE is HIGH, S# is
HIGH between valid commands; Address bus inputs are stable during
DESELECTs; Data bus inputs are switching
I
DD7
a
4,320 4,050 3,960 mA
P1-P3P4-P6P7-P9P10-P12P13-P15

MT18HVF12872Y-53EB1

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Manufacturer:
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MODULE DDR2 SDRAM 1GB 240RDIMM
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