DATASHEET
VERSACLOCK
®
LOW POWER CLOCK GENERATOR IDT5P49EE515
IDT®
VERSACLOCK
®
LOW POWER CLOCK GENERATOR 1
IDT5P49EE515 REV H 101711
Description
The IDT5P49EE515 is a programmable clock generator
intended for low power, battery operated consumer
applications. There are four internal PLLs, each individually
programmable, allowing for up to five unique
non-integer-related frequencies. The frequencies are
generated from a single reference clock. The reference
clock needs to come from a TCXO sine wave input.
A buffered reference Sine wave output clock is supported
with amplitude of 750 mV to 1V, peak to peak.
The IDT5P49EE515 can be programmed through the use
of the I
2
C interfaces. The programming interface enables
the device to be programmed when it is in normal operation
or what is commonly known as in system programmable.
An internal EEPROM allows the user to save and restore
the configuration of the device without having to reprogram
it on power-up.
Each of the four PLLs has an 8-bit reference divider and a
11-bit feedback divider. This allows the user to generate
four unique non-integer-related frequencies. The PLL loop
bandwidth is programmable to allow the user to tailor the
PLL response to the application. For instance, the user can
tune the PLL parameters to minimize jitter generation or to
maximize jitter attenuation. Spread spectrum generation is
supported on one of the PLLs.
There are total three 8-bit output dividers. The outputs are
connected to the PLLs via the switch matrix. The switch
matrix allows the user to route the PLL outputs to any
output bank. This feature can be used to simplify and
optimize the board layout. In addition, each output's slew
rate and enable/disable function can be programmed.
Target Applications
•
Smart Mobile Handset
• Personal Navigation Device (PND)
• Camcorder
• DSC
• Portable Game Console
• Personal Media Player
Features
• Four internal PLLs
• Internal non-volatile EEPROM
• Internal I
2
C EEPROM master interface
• FAST (400kHz) mode I
2
C serial interfaces
• Input Frequencies
– TCXO: 10 MHz to 40 MHz
• Two buffered Sine wave output at 750 mV to 1Vpp
• Output Frequency Ranges: kHz to 100 MHz
• Each PLL has an 8-bit reference divider and a 11-bit
feedback-divider
• 8-bit output-divider blocks
• I/O Standards:
– Outputs - 1.8V/2.5V/3.3 V LVTTL/ LVCMOS
• 2 independent adjustable VDDO groups.
• Programmable Slew Rate Control
• Programmable Loop Bandwidth Settings
• Programmable output inversion to reduce bimodal jitter
• Individual output enable/disable
• Power-down/Sleep mode
– 10μA max in power down mode
• 1.8V VDD Core Voltage
• Available in 20pin 3x3mm QFN packages
• -40 to +85 C Industrial Temp operation
