IDT5P49EE515
VERSACLOCK
®
LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR
IDT®
VERSACLOCK
®
LOW POWER CLOCK GENERATOR 5
IDT5P49EE515 REV H 101711
PLL Features and Descriptions
PLL Block Diagram
Reference Pre-Divider, Reference Divider,
Feedback-Divider and Post-Divider
Each PLL incorporates an 8-bit reference-scaler and a
11-bit feedback divider which allows the user to generate
four unique non-integer-related frequencies. PLLA and
PLLD each have a feedback pre-divider that provides
additional multiplication for kHz reference clock
applications. Each output divider supports 8-bit post-divider.
The following equation governs how the output frequency is
calculated.
Where F
IN
is the reference frequency, XDIV is the feedback
pre-divider value, M is the feedback-divider value, D is the
reference divider value, ODIV is the total post-divider value,
and F
OUT
is the resulting output frequency. Programming
any of the dividers may cause glitches on the outputs.
LOOP FILTER
The loop filter for each PLL can be programmed to optimize
the jitter performance. The low-pass frequency response of
the PLL is the mechanism that dictates the jitter transfer
characteristics. The loop bandwidth can be extracted from
the jitter transfer. A narrow loop bandwidth is good for jitter
attenuation while a wide loop bandwidth is best for low jitter
generation. The specific loop filter components that can be
programmed are the resistor via the RZ[4:0] bits, zero
capacitor via the CZ[2:0] bits, pole capacitor via the CP[1:0]
bits, and the charge pump current via the IP#[2:0] bits.
The following equations govern how the loop filter is set:
Zero capacitor (Cz) = 280pF
Pole capacitor (Cp) = 30pF
Charge pump (Ip) = IP#[2:0] uA
VCO gain (K
VCO) = 300MHz/V * 2π
Ref-Divider
(D) Values
Feedback
Pre-Divider
(XDIV)
Values
Feedback
(M) Values
Programmable
Loop Bandwidth
Spread Spectrum
Generation Capability
PLLA 1 - 255 1 or 4 6 - 2047 Yes No
PLLB 1 - 255 4 6 - 2047 Yes Yes
PLLC 1 - 255 1 or 8 bit divide 6 - 2047 Yes No
PLLD 1 - 255 1 or 4 6 - 2047 Yes No
( )
F
OUT
=
XDIV*M
D
F
IN
*
ODIV
(Eq. 2)
