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PTN3392BS,518

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
PTN3392 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 5 June 2014 13 of 32
NXP Semiconductors
PTN3392
2-lane DisplayPort to VGA adapter IC
7.4.1 S0 = logic 0
If S0 is left open-circuit (internal pull-down) (DisplayPort v1.1a compliant behavior),
PTN3392 behaves as stated in VESA DisplayPort v1.1a, sections 7 and 8. PTN3392 will
keep HPD LOW during its internal initialization sequence after power-up. It will then
update DPCD register SINK_COUNT to the expected value, depending if a VGA monitor
is detected or not, and will then assert HPD HIGH whatever is the value of SINK_COUNT
register. Each time PTN3392 detects a change in the VGA monitor connection status, it
updates the SINK_COUNT register accordingly, set
DOWNSTREAM_PORT_STATUS_CHANGED register bit to 1 and generate IRQ_HPD
pulse to signal the source about the status change. Refer to Figure 3
, S0 = LOW
flowchart.
7.4.2 S0 = logic 1
If S1 is tied to HIGH with external pull-up (best interoperability behavior), the PTN3392 will
keep HPD LOW during its internal initialization sequence after power-up. It then waits for
a VGA monitor to be connected downstream before asserting HPD HIGH to force source
waiting for a VGA monitor before starting protocol negotiations. If a VGA monitor is
disconnected during normal operations, PTN3392 asserts HPD LOW so that the source
considers that no sink device is connected anymore. Refer to Figure 3
, S0 = HIGH
flowchart.
7.5 EDID handling
Figure 4 shows a DisplayPort-to-analog video converter (or dongle) situated between the
DisplayPort source and a VGA monitor. The PTN3392 converts a DP I
2
C Over AUX
request to I
2
C on the monitor's DDC bus. The monitor's EDID read data is then returned to
the DP source via an I
2
C Over AUX response issued by the PTN3392.
It is the responsibility of the source to choose only video modes which are declared in the
EDID and to adjust the DisplayPort link capabilities (link rate and lane count) to provide
the necessary video bandwidth. The PTN3392 does not cache or modify the EDID to
match the capabilities of the DisplayPort link data.
If the DisplayPort source drives display modes that are not specified in the EDID mode
list, the PTN3392 does not detect such conditions, and displays at its output what it is
presented by the DisplayPort source.
Fig 4. DisplayPort to VGA adapter IC (dongle) sits between the DisplayPort source and a
VGA monitor with EDID
DP Tx
002aae039
box-to-box
DisplayPort
source device
DP Rx
with DPCD
VIDEO DAC
DisplayPort to VGA adapter IC
box-to-box
legacy
VGA DISPLAY
WITH EDID
sink device
PTN3392 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 5 June 2014 14 of 32
NXP Semiconductors
PTN3392
2-lane DisplayPort to VGA adapter IC
7.6 Triple 8-bit video DACs and VGA outputs
The triple 8-bit video DACs output a 700 mV (peak-to-peak) analog video output signal
into 37.5 load, as is the case of a doubly terminated 75 cable. The DAC is capable of
supporting the maximum pixel rate supported by a two-lane DP link (240 MHz).
The PTN3392 generates the RGB video timing and synchronization signals, RGB signals
are then sent to the DACs for conversion to analog signals.
7.6.1 DAC reference resistor
An external reference resistor must be connected between pin RSET and analog ground.
This resistor sets the reference current which determines the analog output level, and is
specified as 1.2 k with a 1 % tolerance. This value allows a 0.7 V (peak-to-peak) output
into a 37.5 load, such as a double-terminated 75 coaxial cable.
8. Power-up and reset
PTN3392 has built-in power-on reset circuitry which automatically sequences the part
through reset and initialization.
For proper behavior, a capacitor should be connected from the RESET_N pin to ground to
slow down the internal reset pulse; 1 F capacitance is recommended.
Before link is established, the PTN3392 holds VSYNC and HSYNC signals LOW and
blanks the RGB signals.
While the PTN3392 performs initialization,
• The HPD signal is driven LOW, to indicate to the DisplayPort source that the
PTN3392 is not ready for link communication
• The RED, GRN, BLU and complementary outputs (RED_N, GRN_N, BLU_N) are
disabled
• The VSYNC and HSYNC outputs are driven LOW
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PTN3392 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 5 June 2014 15 of 32
NXP Semiconductors
PTN3392
2-lane DisplayPort to VGA adapter IC
9. Application design-in information
(1) 1 F is recommended.
(2) Example of external DC-to-DC regulator.
Fig 5. Application diagram
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

PTN3392BS,518

Mfr. #:
Buy PTN3392BS,518
Manufacturer:
NXP Semiconductors
Description:
Interface - Specialized DisplayPort-VGA 3.3V
Lifecycle:
New from this manufacturer.
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