PTN3392 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 5 June 2014 8 of 32
NXP Semiconductors
PTN3392
2-lane DisplayPort to VGA adapter IC
7. Functional description
Referring to Figure 1 “Functional diagram”, the PTN3392 converts the DisplayPort
AC-coupled high-speed differential signaling protocol into a VESA VSIS 1.2 compliant
analog VGA signaling. The PTN3392 integrates a DisplayPort receiver (according to
VESA DisplayPort v1.1a specification, Ref. 1
) and a high-speed triple 8-bit video
digital-to-analog converter that supports display resolution from VGA to WUXGA (see
Table 5 “
Display resolution and pixel clock rate
[1]
”), up to a pixel clock rate of 240 MHz.
The PTN3392 supports one or two DisplayPort v1.1a Main Link lanes operating at either
in 2.7 Gbit/s or 1.62 Gbit/s per lane. The PTN3392 can drive up to 100 feet of analog
video cable.
The DisplayPort receiver comprises the following functional blocks:
• Main Link
• AUX CH (Auxiliary Channel)
• DPCD (DisplayPort Configuration Data)
• Monitor detection
• EDID handling
• Video DAC
The RGB video data with corresponding synchronization references is extracted from the
main stream video data. Main stream video attribute information is also extracted. This
information is inserted once per video frame during the vertical blanking period by the
DisplayPort source. The attributes describe the main video stream format in terms of
geometry, timing, and color format. The original clock and video stream are derived from
these main link data.
The PTN3392 internal DPCD registers can be accessed by the source via the auxiliary
channel. The monitor’s DDC control bus may also be controlled via the auxiliary channel.
A bridging conversion block translates the input DisplayPort auxiliary channel signals from
the source side to the DDC signals on the sink side. The PTN3392 passes through
sink-side status change (e.g., hot-plug events) to the source side, through HPD interrupts
and DPCD registers.
7.1 DisplayPort Main Link
The DisplayPort main link consists of doubly terminated, AC-coupled differential pair. The
50 internally calibrated termination resistors are integrated inside PTN3392.
The PTN3392 supports HBR at 2.7 Gbit/s and RBR at 1.62 Gbit/s per lane.
7.2 DisplayPort auxiliary channel
The AUX CH is a half-duplex, bidirectional channel between DisplayPort transmitter and
receiver. It consists of one differential pair transporting self-clocked data at 1 Mbit/s. The
PTN3392 integrates the AUX CH replier (or slave), and responds to transactions initiated
by the DisplayPort source AUX CH requester (or master).
The AUX CH uses the Manchester-II code for the self-clocked transmission of signals;
every ‘zero’ is represented by LOW-to-HIGH transition, and ‘one’ represented by
HIGH-to-LOW transition, in the middle of the bit time.
