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PTN3392BS,518

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
PTN3392 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 5 June 2014 4 of 32
NXP Semiconductors
PTN3392
2-lane DisplayPort to VGA adapter IC
5. Functional diagram
Fig 1. Functional diagram
002aae032
DIFF
RCV
CDR,
S2P
RX PHY
ANALOG
SUBSYSTEM
DIFF
RCV
CDR,
S2P
RCV
PTN3392
DRV
MANCHESTER
CODEC
RX DIGITAL SUBSYSTEM
10b/8b
DE-SCRAM
INTERFACE DE-SKEWING
10b/8b
DE-SCRAM
RX PHY DIGITAL
AUX COMMAND
LEVEL MODULE
RX ACLI
DPCD
REGISTERS
I
2
C-BUS
MASTER
FLASH MCU
CONTROL
TIME
CONV.
ISOCHRONOUS LINK
TIMING RECOVERY
MAIN
STREAM
DAC
DAC
DAC
R[7:0]
G[7:0]
B[7:0]
VGA
OUTPUT
H, V
sync
VIDEO DAC SUBSYSTEM
R
G
B
HSYNC
VSYNC
SCL
SDA
V
bias
V
bias
V
bias
MONITOR
PRESENCE
DETECT
lane 0
lane 1
AUX
PTN3392 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 5 June 2014 5 of 32
NXP Semiconductors
PTN3392
2-lane DisplayPort to VGA adapter IC
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 2. Pin configuration for HVQFN48
002aae033
PTN3392BS
RED
SCL
VDD_IO
OSC_IN
TDI OSC_OUT
TRST_N GNDD
TMS GNDD
GND_IO LDOCAP_CORE
TDO VDDD
TCK VDDD
VDDA_DP S0
HPD S1
CLK_O S2
RESET_N S3
SDA
VSYNC
HSYNC
BLU
VDD_DAC
VDD_DAC
BLU_N
GRN_N
GRN
RSET
GND_DAC
RED_N
GNDA_DP1
ML1_N
ML1_P
GNDA_DP0
ML0_N
ML0_P
RRX
GNDA
AUX_N
AUX_P
LDOCAP_AUX
VDDA
12 25
11 26
10 27
9 28
8 29
7 30
6 31
5 32
4 33
3 34
2 35
1 36
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
terminal 1
index area
Transparent top view
Table 3. Pin description
Symbol Pin Type Description
VDDD 32, 31 power digital core 3.3 V supply
VDDA 37 power analog AUX, bias and PLL 3.3 V supply
voltage
VDDA_DP 4 power analog 3.3 V supply for DisplayPort receiver
module
VDD_IO 12 power I/O 3.3 V supply voltage
VDD_DAC 17, 18 power analog 3.3 V supply for DAC
GND_IO
[1]
7 power I/O supply ground
GND_DAC
[1]
23 power analog ground for DAC
GNDA_DP0
[1]
45 power analog ground for DisplayPort Lane0
GNDA_DP1
[1]
48 power analog ground for DisplayPort Lane1
GNDA
[1]
41 power analog AUX, bias and PLL supply ground
GNDD
[1]
28, 29 power digital core supply ground
PTN3392 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 5 June 2014 6 of 32
NXP Semiconductors
PTN3392
2-lane DisplayPort to VGA adapter IC
DisplayPort
ML0_P 43 self-biasing
differential input
DisplayPort main lane signal lane 0, positive
ML0_N 44 self-biasing
differential input
DisplayPort main lane signal lane 0, negative
ML1_P 46 self-biasing
differential input
DisplayPort main lane signal lane 1, positive
ML1_N 47 self-biasing
differential input
DisplayPort main lane signal lane 1, negative
AUX_P 39 self-biasing
differential
input/output
DisplayPort auxiliary channel signal, positive
AUX_N 40 self-biasing
differential
input/output
DisplayPort auxiliary channel signal, negative
HPD 3 3.3 V TTL
single-ended output
Hot-plug detect
RGB DAC outputs
BLU 16 analog output ‘blue’ current analog output
BLU_N 19 analog output ‘blue’ current complementary analog output
GRN 21 analog output ‘green’ current analog output
GRN_N 20 analog output ‘green’ current complementary analog output
RED 25 analog output ‘red’ current analog output
RED_N 24 analog output ‘red’ current complementary analog output
RSET 22 analog input/output DAC full-scale current control resistor.
Pull down to ground by an external
1.2 k1 % resistor.
DDC
SCL 11 single-ended 5 V
open-drain DDC I/O
5 V sink-side DDC clock I/O. Pulled up by
1.2 k external resistor to 5 V.
SDA 13 single-ended 5 V
open-drain DDC I/O
5 V sink-side DDC data I/O. Pulled up by
1.2 k external resistor to 5 V.
Monitor-side sync
HSYNC 15 single-ended 3.3 V
TTL output
horizontal sync signal to monitor; serial
resistance of 36 is recommended.
VSYNC 14 single-ended 3.3 V
TTL output
vertical sync signal to monitor; serial
resistance of 36 is recommended.
JTAG
TCK 5 input JTAG clock input
TDO 6 output JTAG data output
TMS 8 input JTAG mode select input
TRST_N 9 input JTAG reset (active LOW) input
TDI 10 input JTAG data input
Table 3. Pin description
…continued
Symbol Pin Type Description
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

PTN3392BS,518

Mfr. #:
Buy PTN3392BS,518
Manufacturer:
NXP Semiconductors
Description:
Interface - Specialized DisplayPort-VGA 3.3V
Lifecycle:
New from this manufacturer.
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