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LPC2129FBD64/01,15

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46
LPC2109_2119_2129 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 14 June 2011 7 of 46
NXP Semiconductors
LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers
P0[15]/RI1/EINT2 45 I RI1 — Ring Indicator input for UART1.
I EINT2 — External interrupt 2 input.
P0[16]/EINT0/
MAT0[2]/CAP0[2]
46 I EINT0 — External interrupt 0 input.
O MAT0[2] — Match output for Timer 0, channel 2.
I CAP0[2] — Capture input for Timer 0, channel 2.
P0[17]/CAP1[2]/
SCK1/MAT1[2]
47 I CAP1[2] — Capture input for Timer 1, channel 2.
I/O SCK1 — Serial Clock for SPI1/SSP
[1]
. SPI clock output from master or input to
slave.
O MAT1[2] — Match output for Timer 1, channel 2.
P0[18]/CAP1[3]/
MISO1/MAT1[3]
53 I CAP1[3] — Capture input for Timer 1, channel 3.
I/O MISO1 — Master In Slave Out for SPI1/SSP
[1]
. Data input to SPI master or data
output from SPI slave.
O MAT1[3] — Match output for Timer 1, channel 3.
P0[19]/MAT1[2]/
MOSI1/CAP1[2]
54 O MAT1[2] — Match output for Timer 1, channel 2.
I/O MOSI1 — Master Out Slave In for SPI1/SSP
[1]
. Data output from SPI master or data
input to SPI slave.
I CAP1[2] — Capture input for Timer 1, channel 2.
P0[20]/MAT1[3]/
SSEL1/EINT3
55 O MAT1[3] — Match output for Timer 1, channel 3.
I SSEL1 — Slave Select for SPI1/SSP
[1]
. Selects the SPI interface as a slave.
I EINT3 — External interrupt 3 input.
P0[21]/PWM5/
CAP1[3]
1OPWM5 — Pulse Width Modulator output 5.
I CAP1[3] — Capture input for Timer 1, channel 3.
P0[22]/CAP0[0]/
MAT0[0]
2ICAP0[0] — Capture input for Timer 0, channel 0.
O MAT0[0] — Match output for Timer 0, channel 0.
P0[23]/RD2 3 I CAN2 receiver input (not available on LPC2109).
P0[24]/TD2 5 O CAN2 transmitter output (not available on LPC2109).
P0[25]/RD1 9 I CAN1 receiver input.
P0[27]/AIN0/
CAP0[1]/MAT0[1]
11 I AIN0 — A/D converter, input 0. This analog input is always connected to its pin.
I CAP0[1] — Capture input for Timer 0, channel 1.
O MAT0[1] — Match output for Timer 0, channel 1.
P0[28]/AIN1/
CAP0[2]/MAT0[2]
13 I AIN1 — A/D converter, input 1. This analog input is always connected to its pin.
I CAP0[2] — Capture input for Timer 0, channel 2.
O MAT0[2] — Match output for Timer 0, channel 2.
P0[29]/AIN2/
CAP0[3]/MAT0[3]
14 I AIN2 — A/D converter, input 2. This analog input is always connected to its pin.
I CAP0[3] — Capture input for Timer 0, Channel 3.
O MAT0[3] — Match output for Timer 0, channel 3.
P0[30]/AIN3/
EINT3/CAP0[0]
15 I AIN3 — A/D converter, input 3. This analog input is always connected to its pin.
I EINT3 — External interrupt 3 input.
I CAP0[0] — Capture input for Timer 0, channel 0.
P1[0] to P1[31] I/O Port 1 is a 32-bit bidirectional I/O port with individual direction controls for each bit.
The operation of port 1 pins depends upon the pin function selected via the Pin
Connect Block. Pins 0 through 15 of port 1 are not available.
Table 3. Pin description
…continued
Symbol Pin Type Description
LPC2109_2119_2129 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 14 June 2011 8 of 46
NXP Semiconductors
LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers
P1[16]/
TRACEPKT0
16 O Trace Packet, bit 0. Standard I/O port with internal pull-up.
P1[17]/
TRACEPKT1
12 O Trace Packet, bit 1. Standard I/O port with internal pull-up.
P1[18]/
TRACEPKT2
8 O Trace Packet, bit 2. Standard I/O port with internal pull-up.
P1[19]/
TRACEPKT3
4 O Trace Packet, bit 3. Standard I/O port with internal pull-up.
P1[20]/
TRACESYNC
48 O Trace Synchronization. Standard I/O port with internal pull-up.
Note: LOW on this pin while RESET
is LOW, enables pins P1[25:16] to operate as
Trace port after reset.
P1[21]/
PIPESTAT0
44 O Pipeline Status, bit 0. Standard I/O port with internal pull-up.
P1[22]/
PIPESTAT1
40 O Pipeline Status, bit 1. Standard I/O port with internal pull-up.
P1[23]/
PIPESTAT2
36 O Pipeline Status, bit 2. Standard I/O port with internal pull-up.
P1[24]/
TRACECLK
32 O Trace Clock. Standard I/O port with internal pull-up.
P1[25]/EXTIN0 28 I External Trigger Input. Standard I/O with internal pull-up.
P1[26]/RTCK 24 I/O Returned Test Clock output. Extra signal added to the JTAG port. Assists debugger
synchronization when processor frequency varies. Bidirectional pin with internal
pull-up.
Note: LOW on this pin while RESET
is LOW, enables pins P1[31:26] to operate as
Debug port after reset.
P1[27]/TDO 64 O Test Data out for JTAG interface.
P1[28]/TDI 60 I Test Data in for JTAG interface.
P1[29]/TCK 56 I Test Clock for JTAG interface. This clock must be slower than
1
⁄
6
of the CPU clock
(CCLK) for the JTAG interface to operate.
P1[30]/TMS 52 I Test Mode Select for JTAG interface.
P1[31]/TRST
20 I Test Reset for JTAG interface.
TD1 10 O CAN1 transmitter output.
RESET
57 I External reset input; a LOW on this pin resets the device, causing I/O ports and
peripherals to take on their default states, and processor execution to begin at
address 0. TTL with hysteresis, 5 V tolerant.
XTAL1 62 I Input to the oscillator circuit and internal clock generator circuits.
XTAL2 61 O Output from the oscillator amplifier.
V
SS
6, 18, 25,
42, 50
I Ground: 0 V reference.
V
SSA
59 I Analog ground; 0 V reference. This should nominally be the same voltage as V
SS
,
but should be isolated to minimize noise and error.
V
SSA(PLL)
58 I PLL analog ground; 0 V reference. This should nominally be the same voltage as
V
SS
, but should be isolated to minimize noise and error.
V
DD(1V8)
17, 49 I 1.8 V core power supply; this is the power supply voltage for internal circuitry.
Table 3. Pin description …continued
Symbol Pin Type Description
LPC2109_2119_2129 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 14 June 2011 9 of 46
NXP Semiconductors
LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers
[1] SSP interface available on LPC2109/01, LPC2119/01, and LPC2129/01 only.
V
DDA(1V8)
63 I Analog 1.8 V core power supply; this is the power supply voltage for internal
circuitry. This should be nominally the same voltage as V
DD(1V8)
but should be
isolated to minimize noise and error.
V
DD(3V3)
23, 43, 51 I 3.3 V pad power supply; this is the power supply voltage for the I/O ports.
V
DDA(3V3)
7 I Analog 3.3 V pad power supply; this should be nominally the same voltage as
V
DD(3V3)
but should be isolated to minimize noise and error.
Table 3. Pin description
…continued
Symbol Pin Type Description
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46

LPC2129FBD64/01,15

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Buy LPC2129FBD64/01,15
Manufacturer:
NXP Semiconductors
Description:
ARM Microcontrollers - MCU ARM7 256KF/16KR/CAN
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