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AD7650
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CIRCUIT INFORMATION
The AD7650 is a very fast, low power, single supply, precise
16-bit analog-to-digital converter (ADC). The AD7650 features
different modes to optimize performances according to the
applications.
In warp mode, the AD7650 is capable of converting 570,000
samples per second (570 kSPS).
The AD7650 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any pipe-
line or latency, making it ideal for multiple multiplexed channel
applications.
The AD7650 can be operated from a single 5 V supply and be
interfaced to either 5 V or 3 V digital logic. It is housed in 48-lead
LQFP or in a tiny 48-LFCSP packages that save space and allows
flexible configurations as either serial or parallel interface. The
AD7650 is pin-to-pin compatible with the AD7664.
CONVERTER OPERATION
The AD7650 is a successive-approximation analog-to-digital
converter based on a charge redistribution DAC. Figure 3 shows
the simplified schematic of the ADC. The capacitive DAC consists
of an array of 16 binary weighted capacitors and an additional
“LSB” capacitor. The comparator’s negative input is connected to
a “dummy” capacitor of the same value as the capacitive DAC array.
During the acquisition phase, the common terminal of the array
tied to the comparator’s positive input is connected to AGND via
SW
A
. All independent switches are connected to the analog input
IN+. Thus, the capacitor array is used as a sampling capacitor
and acquires the analog signal on IN+ input. Similarly, the
“dummy” capacitor acquires the analog signal on IN– input.
When the CNVST input goes low, a conversion phase is initiated.
When the conversion phase begins, SW
A
and SW
B
are opened
first. The capacitor array and the “dummy” capacitor are then
disconnected from the inputs and connected to the REFGND
input. Therefore, the differential voltage between IN+ and
IN– captured at the end of the acquisition phase is applied to
the comparator inputs, causing the comparator to become unbal-
anced. By switching each element of the capacitor array between
REFGND or REF, the comparator input varies by binary-
weighted voltage steps (V
REF
/2, V
REF
/4,...V
REF
/65536). The
control logic toggles these switches, starting with the MSB first,
to bring the comparator back into a balanced condition. After
the completion of this process, the control logic generates the
ADC output code and brings BUSY output low.
Modes of Operation
The AD7650 features three modes of operations, Warp, Normal,
and Impulse. Each of these modes is more suitable for specific
applications.
The Warp mode allows the fastest conversion rate up to 570 kSPS.
However, in this mode, and this mode only, the full specified
accuracy is guaranteed only when the time between conversion
does not exceed 1 ms. If the time between two consecutive
conversions is longer than 1 ms, for instance, after power-up,
the first conversion result should be ignored. This mode makes
the AD7650 ideal for applications where both high accuracy and
fast sample rate are required.
The normal mode is the fastest mode (500 kSPS) without any
limitation about the time between conversions. This mode makes the
AD7650 ideal for asynchronous applications such as data acqui-
sition systems, where both high accuracy and fast sample rate are
required. It is selected when both IMPULSE and WARP are low.
The impulse mode, the lowest power dissipation mode, allows
power saving between conversions. When operating at 100 SPS,
for example, it typically consumes only 21 µW. This feature
makes the AD7650 ideal for battery-powered applications.
SW
A
COMP
SW
B
IN+
REF
REFGND
LSB
MSB
32,768C
IN–
16,384C 4C 2C C C
65,536C
CONTROL
LOGIC
SWITCHES
CONTROL
BUSY
OUTPUT
CODE
CNVST
Figure 3. ADC Simplified Schematic
