REV. 0
–15–
AD7650
EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0
t
3
t
1
t
17
t
14
t
19
t
20
t
21
t
24
t
26
t
25
t
27
t
23
t
22
t
16
t
15
D15 D14 D2 D1 D0X
12 3 141516
t
18
BUSY
CS, RD
CNVST
SYNC
SCLK
SDOUT
Figure 14. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)
Usually, because the AD7650 is used with a fast throughput, the
mode master, read during conversion is the most recommended
serial mode when it can be used.
In read-during-conversion mode, the serial clock and data toggle
at appropriate instants which minimize potential feedthrough
between digital activity and the critical conversion decisions.
In read-after-conversion mode, it should be noted that, unlike in
other modes, the signal BUSY returns low after the 16 data bits
are pulsed out and not at the end of the conversion phase which
results in a longer BUSY width.
SLAVE SERIAL INTERFACE
External Clock
The AD7650 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/INT pin is
held high. In this mode, several methods can be used to read the
data. The external serial clock is gated by CS. When CS and
RD are both low, the data can be read after each conversion or
during the following conversion. The external clock can be either a
continuous or discontinuous clock. A discontinuous clock can be
either normally high or normally low when inactive. Figure 15
and Figure 16 show the detailed timing diagrams of these methods.
While the AD7650 is performing a bit decision, it is important
that voltage transients not occur on digital input/output pins or
degradation of the conversion result could occur. This is par-
ticularly important during the second half of the conversion
phase because the AD7650 provides error correction circuitry
that can correct for an improper bit decision made during the
first half of the conversion phase. For this reason, it is recom-
mended that when an external clock is being provided, it is a
discontinuous clock that is toggling only when BUSY is low or,
more importantly, that it does not transition during the latter
half of BUSY high.
External Discontinuous Clock Data Read After Conversion
Though the maximum throughput cannot be achieved using this
mode, it is the most recommended of the serial slave modes.
Figure 15 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
low, the result of this conversion can be read while both CS and
RD are low. The data is shifted out, MSB first, with 16 clock
pulses and is valid on both rising and falling edge of the clock.
Among the advantages of this method, the conversion perfor-
mance is not degraded because there are no voltage transients
on the digital interface during the conversion process.
Another advantage is to be able to read the data at any speed up
to 40 MHz, which accommodates both slow digital host inter-
face and the fastest serial reading.
Finally, in this mode only, the AD7650 provides a “daisy-chain”
feature using the RDC/SDIN input pin for cascading multiple
converters together. This feature is useful for reducing component
count and wiring connections when desired as, for instance, in
isolated multiconverter applications.
An example of the concatenation of two devices is shown in
Figure 17. Simultaneous sampling is possible by using a common
CNVST signal. It should be noted that the RDC/SDIN input is
latched on the edge of SCLK opposite to the one used to shift
out the data on SDOUT. Hence, the MSB of the “upstream”
converter just follows the LSB of the “downstream” converter
on the next SCLK cycle.
