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NTMS7N03R2

P1-P3P4-P6P7-P9
NTMS7N03R2G
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7
I
S
, SOURCE CURRENT
t, TIME
Figure 11. Reverse Recovery Time (t
rr
)
di/dt = 300 A/ms
Standard Cell Density
High Cell Density
t
b
t
rr
t
a
t
rr
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T
C
) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(I
DM
) nor rated voltage (V
DSS
) is exceeded, and that the
transition time (t
r
, t
f
) does not exceed 10 ms. In addition the
total power averaged over a complete switching cycle must
not exceed (T
J(MAX)
− T
C
)/(R
q
JC
).
A power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non−linearly with an increase of peak current in avalanche
and peak junction temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I
DM
), the energy rating is specified at rated
continuous current (I
D
), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 13). Maximum
energy at currents below rated continuous I
D
can safely be
assumed to equal the values indicated.
T
J
, STARTING JUNCTION TEMPERATURE (°C)
E
AS
, SINGLE PULSE DRAIN−TO−SOURC
E
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
AVALANCHE ENERGY (mJ)
25 50 75 100 125
I
D
= 12 A
300
15
0
0
0.1
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1
10
I
D
, DRAIN CURRENT (AMPS)
R
DS(on)
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01
V
GS
= 20 V
SINGLE PULSE
T
C
= 25°C
10
0.1
10 ms
1
100
100
Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″
thick single sided) with one die operating, 10s max.
1 ms
100 ms
10 ms
50
150
200
350
100
250
400
dc
NTMS7N03R2G
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8
TYPICAL ELECTRICAL CHARACTERISTICS
Figure 14. Thermal Response
Figure 15. Diode Reverse Recovery Waveform
di/dt
t
rr
t
a
t
p
I
S
0.25 I
S
TIME
I
S
t
b
t, TIME (s)
Rthja(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE
1
0.1
0.01
D = 0.5
SINGLE PULSE
1.0E−05 1.0E−04 1.0E−03 1.0E−02 1.0E−01 1.0E+00 1.0E+01
0.2
0.1
0.05
0.02
0.01
1.0E+02 1.0E+03
0.001
10
0.0163 W 0.0652 W 0.1988 W 0.6411 W 0.9502 W
72.416 F1.9437 F0.5541 F0.1668 F0.0307 F
Chip
Ambient
Normalized to qja at 10s.
NTMS7N03R2G
www.onsemi.com
9
PACKAGE DIMENSIONS
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
SOIC−8 NB
CASE 751−07
ISSUE AK
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒ
mm
inches
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
SEATING
PLANE
1
4
58
N
J
X 45
_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
B
S
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) Z
S
X
S
M
____
P
UBLICATION ORDERING INFORMATION
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
NTMS7N03R2/D
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your loc
al
Sales Representative
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or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
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expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
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NTMS7N03R2

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ON Semiconductor
Description:
MOSFET N-CH 30V 4.8A 8-SOIC
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