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FDMF3035

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
FDMF3035
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13
SYNCHRONOUS BUCK OPERATING MODES
Continuous Current Mode with Positive Inductor
Current (CCM1)
This condition is typical of a moderate−to−heavily loaded
power stage. During this mode, the inductor current is
always flowing towards the output capacitor. The high− side
MOSFET is hard−switching during the turn−on and turn−off
events. The low−side MOSFET acts a synchronous rectifier.
Continuous Current Mode with Negative Inductor
Current (CCM2)
This operating mode can occur during two situations:
1. A converter load transient may force the power
stage to pull energy from the output capacitors and
deliver the energy back to the input capacitors
(Boost Mode). This situation is common in
synchronous buck applications that require output
voltage load−line positioning.
During this mode, the negative inductor current
(current flowing into FDMF3035 SW node) may
become large and persist for many cycles. This
situation causes the low−side MOSFET to hard
switch and the high−side MOSFET acts as a
synchronous rectifier. It is highly recommended to
check peak SW node voltage stress during any
situation that can generate large negative inductor
currents
2. A power stage that is operating in forced CCM
mode with lighter converter loads. Here, the
inductor peak−to−peak ripple current is greater
than two times the load current and the inductor
current is flowing both positive and negative in a
switching cycle
Discontinuous Current Mode (DCM)
This condition is typical of a lightly loaded power stage.
During DCM, the high−side MOSFET turns on into an
un−energized out filter inductor (i.e. zero inductor current).
The inductor current ramps up during the high− side
MOSFET on−time and is then allowed to ramp back down
to aero amps during the low−side on−time (i.e inductor
current returns to zero every switching cycle.
High−Side Driver
The high−side driver (HDRV) is designed to drive a
floating N−channel MOSFET (Q1). The bias voltage for the
high−side driver is developed by a bootstrap supply circuit,
consisting of the internal Schottky diode and external
bootstrap capacitor (CBOOT). During startup, the SW node
should be held at PGND, allowing CBOOT to charge to
PVCC through the internal bootstrap diode. When the PWM
input goes HIGH, HDRV begins to charge the gate of the
high−side MOSFET (internal GH pin). During this
transition, the charge is removed from the CBOOT and
delivered to the gate of Q1. As Q1 turns on, SW rises to VIN,
forcing the BOOT pin to VIN + VBOOT, which provides
sufficient VGS enhancement for Q1. To complete the
switching cycle, Q1 is turned off by pulling HDRV to SW.
CBOOT is then recharged to PVCC when the SW falls to
PGND. HDRV output is in phase with the PWM input. The
high−side gate is held LOW when the driver is disabled or
the PWM signal is held within the 3−state window for longer
than the 3−state hold−off time, tD_HOLD−OFF.
Low−Side Driver
The low−side driver (LDRV) is designed to drive the
gate−source of a ground−referenced, low−RDS(ON),
N−channel MOSFET (Q2). The bias for LDRV is internally
connected between the PVCC and AGND. When the driver
is enabled, the driver output is 180° out of phase with the
PWM input. When the driver is disabled (FCCM = 0 V),
LDRV is held LOW.
FDMF3035
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14
Figure 28. PWM 3−State Timing Diagram (FCCM Held HIGH)
Inductor
Current
PWM
SW
GL
GH to SW
V
IH_PWM
VIL_PWM
3−State
Window
90%
10%
t
PD_PHGLL
t
D_DEADON
t
PD_PLGHL
t
D_DEADOFF
Less than
t
D_HOLD−OFF
Less than
t
D_HOLD−OFF
3−State
t
HOLD_OFF
Window
3−State
Window
GL / GH
off
GL / GH
off
90%
10%
t
D_DEADON
tPD_PHGLL
t
HOLD_OFF
t
PD_THGHH
t
PD_TLGLH
t
D_HOLD−OFF
t
D_HOLD−OFF
Figure 29. 3−State Timing Diagram
PWM
SW
GL
FCCM
DCM
CCM
(Neg. Inductor
Current)
VIL_PWM
VIH_FCCM
10%
V
OUT
[ HS turn−on in DCM ]
Delay from PWM going HIGH
to HS V
GS
HIGH
GH to SW
VIH_PWM
Inductor
Current
DCM
CCM operation with
positive inductor current
CCM operation with
negative inductor current
DCM operation allowed:
Diode Emulation using the GL
(LS MOSFET V
GS
) to eliminate
negative inductor current
FCCM used
to control
negative
inductor
current
t
PD_PHGHH
t
PD_ZCD
Delay from FCCM going
HIGH to LS V
GS
HIGH
t
PD_ZCD
Delay from FCCM going
HIGH to LS V
GS
HIGH
90%
10%
−0.5mV
SW
(zoom)
V
IN
DCM
VIL_FCCM
FCCM used to
place driver IC
is low power
shutdown
mode
CCM
t
PS_EXIT
CCM
(Pos. Inductor
Current)
FDMF3035
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15
APPLICATION INFORMATION
Decoupling Capacitor for PVCC & VCC
For the supply inputs (PVCC and VCC pins), local
decoupling capacitors are required to supply the peak
driving current and to reduce noise during switching
operation. Use at least 0.68 ~ 1 mF / 0402 ~ 0603 / X5R
~ X7R multi−layer ceramic capacitors for both power rails.
Keep these capacitors close to the PVCC and VCC pins and
PGND and AGND copper planes. If the de−coupling
capacitors need to be located on the bottom side of board,
place through−hole vias on each pad connecting top side and
bottom side PVCC and VCC nodes with low impedance
current paths, see Figure 31 and Figure 32.
The supply voltage range on PVCC and VCC is 4.5 V
~ 5.5 V, and typically 5 V for normal applications.
R−C Filter on VCC
The PVCC pin provides power to the gate drive of the
high−side and low−side power MOSFETs. In most cases,
PVCC can be connected directly to VCC, which is the pin
that provides power to the analog and logic blocks of the
driver. To avoid switching noise injection from PVCC into
VCC, a filter resistor can be inserted between PVCC and
VCC decoupling capacitors.
Recommended filter resistor value range is 0 ~ 4.7 W,
typically 0 W for most applications.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor
(C
BOOT
). A bootstrap capacitor of 0.1 ~ 0.22 mF / 0402
~ 0603 / X5R ~ X7R is usually appropriate for most
switching applications. A series bootstrap resistor may be
needed for specific applications to lower high−side
MOSFET switching speed. The boot resistor is required
when the SPS is switching above 15 V V
IN
; when it is
effective at controlling VSW overshoot. R
BOOT
value from
zero to 4.7 W is typically recommended to reduce excessive
voltage spike and ringing on the SW node. A higher R
BOOT
value can cause lower efficiency due to high switching loss
of high−side MOSFET.
Do not add a capacitor or resistor between the BOOT pin
and GND.
PWM (Input)
The PWM pin recognizes three different logic levels from
PWM controller: HIGH, LOW, and 3−state. When the PWM
pin receives a HIGH command, the gate driver turns on the
high−side MOSFET. When the PWM pin receives a LOW
command, the gate driver turns on the low−side MOSFET.
When the PWM pin receives a voltage signal inside of the
3−state window (V
TRI_Window
) and exceeds the 3−state
hold−off time, the gate driver turns off both high−side and
low−side MOSFETs. To recognize the high−impedance
3−state signal from the controller, the PWM pin has an
internal resistor divider from VCC to PWM to AGND. The
resistor divider sets a voltage level on the PWM pin inside
the 3−state window when the PWM signal from the
controller is high−impedance.
FCCM (Input)
When the FCCM pin is set HIGH, the driver IC Zero Cross
Detect (ZCD) comparator is disabled and the high−side and
low−side MOSFETs switch in FCCM (Forced CCM) and
follows the PWM signal. When the FCCM pin is set LOW,
the low−side MOSFET turns off when the SPS driver detects
negative inductor current during the low−side MOSFET
turn−on period. This operating mode is commonly referred
to as diode emulation. The diode emulation feature allows
for higher converter efficiency during light−load condition
and PFM / DCM operation.
Applications that require diode emulation and/or low
shutdown current should actively drive the FCCM pin from
a PWM controller. Do not add any noise filter capacitor on
the FCCM pin.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

FDMF3035

Mfr. #:
Buy FDMF3035
Manufacturer:
ON Semiconductor / Fairchild
Description:
Gate Drivers SMART POWER STAGE MODULE
Lifecycle:
New from this manufacturer.
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