ADT7466
Rev. 2 | Page 25 of 48 | www.onsemi.com
04711-029
7 6 5 4 3 2 1 0
00000001
PROCHOT
PROCHOT
TIMER
(REG. 0x0F)
PROCHOT ASSERTED < OR = 25ms
PROCHOT
ACCUMULATE PROCHOT LOW
ASSERTION TIMES
7 6 5 4 3 2 1 0
00000010
PROCHOT
TIMER
(REG. 0x0F)
PROCHOT ASSERTED > OR = 50ms
PROCHOT
ACCUMULATE PROCHOT LOW
ASSERTION TIMES
7 6 5 4 3 2 1 0
00000101
PROCHOT
TIMER
(REG. 0x0F)
PROCHOT ASSERTED > OR = 125ms
(100ms + 25ms)
Figure 30. PROCHOT
Timer
Figure 30 shows how the
PROCHOT
timer behaves as the
PROCHOT
input is asserted and negated. Bit 0 is set on the first
PROCHOT
assertion that is detected. This bit remains set until
the cumulative
PROCHOT
assertions exceed 50 ms. At this
time, Bit 1 of the
PROCHOT
timer is set, and Bit 0 is cleared.
Bit 0 now reflects timer readings with a resolution of 25 ms.
When using the
PROCHOT
timer, be aware of the following.
After a
PROCHOT
timer read (0x0F):
The contents of the timer are cleared on read.
The PHOT bit (Bit 1) of Status Register 2 is cleared
automatically.
If the
PROCHOT
timer is read during a
PROCHOT
assertion,
the following happens:
The contents of the timer are cleared.
Bit 0 of the
PROCHOT
timer is set to 1 (since a
PROCHOT
assertion is occurring).
The
PROCHOT
timer increments from 0.
If the
PROCHOT
limit (0x1E) = 0x00, the PHOT bit is set.
Generating
ALERT
Interrupts from
PROCHOT
Events
The ADT7466 can generate
ALERT
s when a programmable
PROCHOT
limit is exceeded. This allows the systems designer
to ignore brief, infrequent
PROCHOT
assertions, while
capturing longer
PROCHOT
events that could signify a more
serious thermal problem within the system. Register 0x1E is the
PROCHOT
limit register. This 8-bit register allows a limit from
0 seconds (first
PROCHOT
assertion) to 6.4 seconds to be set
before an
ALERT
is generated. The
PROCHOT
timer value is
compared with the contents of the
PROCHOT
limit register. If
the
PROCHOT
timer value exceeds the
PROCHOT
limit value,
the PHOT bit (Bit 1) of Status Register 2 is set, and an
ALERT
is
generated. The PHOT bit (Bit 1) of Mask Register 2 (0x13)
masks
ALERT
s if this bit is set to 1, although the PHOT bit of
Interrupt Status Register 2 is still set if the
PROCHOT
limit is
exceeded.
Figure 32 is a functional block diagram of the
PROCHOT
timer
limit and associated circuitry. Writing a value of 0x00 to the
PROCHOT
limit register (0x21) causes
ALERT
to be generated
on the first
PROCHOT
assertion. A
PROCHOT
limit value of
0x01 generates an
ALERT
when cumulative
PROCHOT
assertions exceed 50 ms.
ADT7466
Rev. 2 | Page 26 of 48 | www.onsemi.com
CONFIGURING THE ADT7466
THERM
PIN
AS AN OUTPUT
If
PROCHOT
monitoring is not required, Pin 7 can be config-
ured as a
THERM
output by setting Bits 1:0 of Configuration
Register 3 to 01. The user can preprogram system critical thermal
limits. If the temperature exceeds a thermal limit by 0.25°C,
THERM
asserts low. If the temperature is still above the thermal
limit on the next monitoring cycle,
THERM
stays low.
THERM
remains asserted low until the temperature is equal to or below
the thermal limit. Since the temperature for that channel is
measured only every monitoring cycle, once
THERM
asserts, it
is guaranteed to remain low for at least one monitoring cycle.
The
THERM
pin can be configured to assert low if the TH1,
TH2, external or internal temperature
THERM
limits are
exceeded by 0.25°C. The
THERM
limit registers are at locations
0x1F, 0x20, 0x21, and 0x22, respectively.
Figure 32 shows how the
THERM
pin asserts low as an output
in the event of a critical overtemperature.
04711-030
THERM LIMIT
25°C
THERM LIMIT
TEMP
THERM
ADT7466
MONITORING
CYCLE
Figure 31. Asserting THERM
as an Output Based on Tripping THERM Limits
04711-031
7 6 5 4 3 2 1 0
25ms
50ms
100ms
200ms
400ms
800ms
1.6s
3.2s
PROCHOT
SMBALERT
0 1 2 3 4 5 6 7
25ms
50ms
100ms
200ms
400ms
800ms
1.6s
3.2s
PROCHOT TIMER CLEARED
ON READ
PROCHOT TIMER
(REG. 0x0F)
PROCHOT LIMIT
(REG. 0x1E)
COMPARATOR
IN OUT
LATCH
RESET
PHOT BIT 1
MASK REGISTER 2
(REG. 0x13)
1 = MASK
CLEARED ON
READ
STATUS
REGISTER 2
PCHT BIT (BIT 1)
Figure 32. Functional Diagram of the ADT7466 PROCHOT
Monitoring Circuitry
ADT7466
Rev. 2 | Page 27 of 48 | www.onsemi.com
FAN DRIVE
The ADT7466 contains two DACs to control fan speed. The
full-scale output of these DACs is typically 2.2 V @ 2 mA, so
they must be buffered in order to drive 5 V or 12 V fans. The
output voltage of these DACs is controlled by data written to the
DRIVE1 (0x40) and DRIVE2 (0x41) registers.
Since fans do not turn on below a certain drive voltage, a
significant proportion of the DAC range would be unusable;
however, four other registers associated with fan speed control
help the user to avoid this problem.
Fan start-up voltage registers (0x30 and 0x31) determine the
voltage initially applied to the fans at startup. This should be
high enough to ensure that the fans start.
Minimum speed registers (0x32 and 0x33) determine the
minimum voltage that is applied to the fans. This should be
high enough to keep the fans turning and less than the voltage
required to start them.
The speed registers associated with automatic fan speed control
(AFC) are the maximum speed registers (0x34 and 0x35). They
allow the maximum output from the DACs to be limited to less
than the full-scale output.
Some suitable fan drive circuits are shown in Figure 33 and
Figure 34. Basically, voltage amplification is required to boost
the full-scale output of the DAC to 5 V or 12 V, and the
amplifier needs sufficient drive current to meet the drive
requirements of the fan.
Note that as the external transistor increases the open-loop gain
of the op amp, it may be necessary to add a capacitor around
the feedback loop to maintain stability.
04711-032
Q1
2N2219
A
12V
R3
1kΩ
1/4
LM324
A
OUT
R1
10kΩ
R2
12kΩ (5V)
43kΩ (12V)
Figure 33. Fan Drive Circuit with Op Amp and Emitter-Follower
04711-033
Q1
IRF9620
5V OR 12V
1/4
LM324
DAC
R3
100kΩ
R1
10kΩ
R2
12kΩ (5V)
43kΩ (12V)
Figure 34. Fan Drive Circuit with P-Channel MOSFET
PWM OR SWITCH MODE FAN DRIVE
Linear dc speed controllers, such as the ones described
previously, waste power, which is dissipated as heat in the power
transistor. To save power and reduce heat dissipation, it may be
desirable to control the fan speed with a more efficient dc-dc
converter or a pulse width modulated (PWM) speed controller.
In this case, the DRIVE outputs of the ADT7466 provide the
reference voltage for this circuit. To maximize efficiency, the
controller can be switched off completely whenever the Fan 1
drive value falls below the value in the V_FAN_MIN register.
When this happens, the FAN1_ON output goes low.
04711-034
ADT7466
V+
DRIVE1
FAN1 ON
DRIVE
VOLTAGE
SHUTDOWN
DC-DC
OR PWM
FAN SPEED
CONTROLLER
Figure 35. DC-DC or PWM Fan Speed Control
FAN SPEED MEASUREMENT
TACH Inputs
Pin 2 and Pin 4 are tach inputs intended for fan speed
measurement. The ADT7466 can measure the speed of 3-wire
fans. Each 3-wire fan has two supply wires and a tach output wire.
Signal conditioning in the ADT7466 accommodates the slow rise
and fall times typical of fan tachometer outputs. The maximum
input signal range is 0 V to 6.5 V, even when V
CC
is less than 5 V. If
these inputs are supplied from fan outputs that exceed 0 V to 6.5 V,
either resistive attenuation of the fan signal or diode clamping
must be included to keep inputs within an acceptable range.
Monitoring 3-Wire Fans
Figure 36 to Figure 39 show circuits for most common 3-wire
fan tach outputs.
If the fan tach output has a resistive pull-up to V
CC
, it can be
connected directly to the fan input, as shown in Figure 36.
04711-035
FAN DRIVE
V
CC
ADT7466
TACH
TACH
OUTPUT
FAN SPEED
COUNTER
PULLUP
4.7kΩ
TYP.
Figure 36. Fan with Tach Pull-Up to +V
CC

ADT7466ZEVB

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
BOARD EVALUATION ADT7466
Lifecycle:
New from this manufacturer.
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