ADT7466ZEVB Datasheet ADT7466ARQZ-RL7, ADT7466ARQZ, ADT7466ARQZ-REEL | P40-P42

ADT7466

Rev. 2 | Page 40 of 48 | www.onsemi.com

Interrupt Status 2

Table 43. Register 0x11—Interrupt Status Register 2 (Power-On Default = 0x00)

Bit No. Name Read/Write Description

0 OVT Read only Setting this bit to 1 indicates that one of the

THERM

overtemperature limits has been exceeded.

This bit is cleared automatically when the temperature drops below

THERM

− T

HYST

1 PHOT Read only If Pin 7 is configured as the input for

PROCHOT

monitoring, this bit is set when the

PROCHOT

assertion time exceeds the limit programmed in the

PROCHOT

limit register (0x1E).

2 D1 Read only Setting this bit to 1 indicates either an open or a short circuit on the Thermal Diode 1 inputs.

3 D2 Read only Setting this bit to 1 indicates either an open or a short circuit on the Thermal Diode 2 inputs.

4 TH1 Read only Setting this bit to 1 indicates either an open or a short circuit on the TH1 input.

5 TH2 Read only Setting this bit to 1 indicates either an open or a short circuit on the TH2 input.

6 Unused Read only Not used. Reads back 0.

7 Unused Read only Not used. Reads back 0.

Interrupt Mask 1

Table 44. Register 0x12—Interrupt Mask Register 1 (Power-On Default = 0x00)

Bit No. Name Read/Write Description

0 FAN2 Read only Setting this bit masks the Fan 2 interrupt from the

ALERT

output.

1 FAN1 Read only Setting this bit masks the Fan 1 interrupt from the

ALERT

output.

2 LOC Read only Setting this bit masks the local temperature. interrupt from the

ALERT

output.

3 REM Read only Setting this bit masks the remote temperature interrupt from the

ALERT

output.

4 V

Read only Setting this bit masks the V

interrupt from the

ALERT

output.

5 AIN2(TH2) Read only Setting this bit masks the AIN2(TH2) interrupt from the

ALERT

output.

6 AIN1

/TH1/REM2

Read only Setting this bit masks the AIN1(TH1)/REM2 interrupt from the

ALERT

output.

7 OOL Read only Setting this bit masks the OOL interrupt from the

ALERT

output.

Interrupt Mask 2

Table 45. Register 0x13—Interrupt Mask Register 2 (Power-On Default = 0x00)

Bit No. Name Read/Write Description

0 OVT Read only

Setting this bit masks the OVT interrupt from

ALERT

output.

1 PHOT Read only

Setting this bit masks the

THERM

interrupt from

ALERT

output.

2 D1 Read only

Setting this bit masks the Thermal Diode 1 fault interrupt from

ALERT

output.

3 D2 Read only

Setting this bit masks Thermal Diode 2 fault interrupt from

ALERT

output.

4 TH1 Read only

Setting this bit masks the TH1 fault interrupt from

ALERT

output.

5 TH2 Read only

Setting this bit masks the TH2 fault interrupt from

ALERT

output.

6 Unused Read only Not used. Reads back 0.

7 Unused Read only Not used. Reads back 0.

ADT7466

Rev. 2 | Page 41 of 48 | www.onsemi.com

Voltage L imit

Setting the Configuration Register 1 lock bit has no effect on these registers.

High limits: An interrupt is generated when a value exceeds its high limit (> comparison).

Low limits: An interrupt is generated when a value is equal to or below its low limit (≤ comparison).

Table 46. Voltage Limit Registers

0x14 Read/Write AIN1(TH1)/REM2 low limit. 0x00

0x15 Read/Write AIN1(TH1)/REM2 high limit. 0xFF

0x16 Read/Write AIN2(TH2) low limit. 0x00

0x17 Read/Write AIN2(TH2) high limit. 0xFF

0x18 Read/Write V

low limit. 0x00

0x19 Read/Write V

high limit. 0xFF

Temperature Limit

Setting the Configuration Register 1 lock bit has no effect on these registers. When the temperature readings are in offset binary format,

an offset of 64 degrees (0x40 or 0100000) must be added to all temperature and

THERM

limits. For example, if the limit is 50°C the

actual programmed limit is 114.

High limits: An interrupt is generated when a value exceeds its high limit (> comparison).

Low limits: An interrupt is generated when a value is equal to or below its low limit (≤ comparison).

Table 47. Temperature Limit Registers

0x1A Read/Write Remote 1 Temperature low limit. 0x00

0x1B Read/Write Remote 1 Temperature high limit. 0x7F

0x1C Read/Write Local temperature low limit. 0x00

0x1D Read/Write Local temperature high limit. 0x7F

PROCHOT

Limit

This is an 8-bit limit with a resolution of 22.76 ms allowing

PROCHOT

assertion limits of 45.52 ms to 5.82 seconds to be programmed. If

the

PROCHOT

assertion time exceeds this limit, Bit 1 of Interrupt Status Register 2 (0x11) is set. If the limit value is 0x00, an interrupt is

generated immediately upon assertion of the

THERM

input.

Table 48. Register 0x1E—

PROCHOT

Limit Register (Power-On Default = 0x00)

Bit No. Name Read/Write Description

7:0 LIMT Read/Write Sets maximum

PROCHOT

assertion length allowed before an interrupt is generated.

ADT7466

Rev. 2 | Page 42 of 48 | www.onsemi.com

THERM Limit

If any temperature measured exceeds its

THERM

limit, both DRIVE outputs drive their fans at maximum output. This is a failsafe

mechanism incorporated to cool the system in the event of a critical overtemperature. It also ensures some level of cooling in the event

that software or hardware locks up. If set to 0x00, this feature is disabled. The DRIVE output remains at 0xFF until the temperature drops

below

THERM

limit − hysteresis. If the

THERM

pin is programmed as an output, exceeding these limits by 0.25°C can cause the

THERM

pin to assert low as an output.

These registers become read only when the Configuration Register 1 lock bit is set to 1. Additional attempts to write to these registers

have no effect.

Table 49. THERM Limit Registers

0x1F Read/Write AIN1/TH1REM2

THERM

limit. 0x64 (100°C)

0x20 Read/Write AIN2(TH2)

THERM

limit. 0x64 (100°C)

0x21 Read/Write Remote 1

THERM

limit. 0x64 (100°C)

0x22 Read/Write Local

THERM

limit. 0x64 (100°C)

Temperature Offset

These registers contain an 8-bit, twos complement offset value that is automatically added to or subtracted from the temperature reading

to compensate for any systematic errors such as those caused by noise pickup. LSB value = 1°C.

This register becomes read only when the Configuration Register 1 lock bit is set to 1. Additional attempts to write to this register have no

effect.

Table 50. Temperature Offset Registers

0x24 Read/Write AIN1(TH1)/REM2 offset. 0x00

0x25 Read/Write AIN2(TH2) offset. 0x00

0x26 Read/Write Remote 1 offset. 0x00

0x27 Read/Write Local offset. 0x00

TMIN

These registers contain the TMIN temperatures for automatic fan control (AFC). These are the temperatures above which the fan starts to

operate. The data format is either binary or offset binary, the same as the temperature reading, depending on which option is chosen by

setting or clearing Bit 7 of Configuration Register 1.

These registers become read only when the Configuration Register 1 lock bit is set to 1. Additional attempts to write to these registers

have no effect.

Table 51. TMIN Registers

0x28 Read/Write AIN1(TH1)/REM2 T

MIN

. 0x5A (90°C)

0x29 Read/Write AIN2(TH2) T

MIN

. 0x5A (90°C)

0x2A Read/Write Remote 1 T

MIN

. 0x5A (90°C)

0x2B Read/Write Local T

MIN

. 0x5A (90°C)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48

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