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85408BGILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
1©2016 Integrated Device Technology, Inc. Revision C, February 23, 2016
General Description
The 85408I is a low skew, high performance 1-to-8
Differential-to-LVDS Clock Distribution Chip. The 85408I CLK, nCLK
pair can accept most differential input levels and translates them to
3.3V LVDS output levels. Utilizing Low Voltage Differential Signaling
(LVDS), the 85408I provides a low power, low noise, low skew,
point-to-point solution for distributing LVDS clock signals.
Guaranteed output and part-to-part skew specifications make the
85408I ideal for those applications demanding well defined
performance and repeatability.
Features
• Eight differential LVDS output pairs
• One differential clock input pair
• CLK, nCLK can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Maximum output frequency: 700MHz
• Translates any differential input signal (LVPECL, LVHSTL, SSTL,
HCSL) to LVDS levels without external bias networks
• Translates any single-ended input signal to LVDS with resistor
bias on nCLK input
• Multiple output enable inputs for disabling unused outputs
in reduced fanout applications
• Additive phase jitter, RMS: 167fs (typical)
• Output skew: 50ps (maximum)
• Part-to-part skew: 550ps (maximum)
• Propagation delay: 2.4ns (maximum)
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nQ6
Q6
nQ5
Q5
nQ4
Q4
nQ3
Q3
nQ2
Q2
nQ1
Q1
Q7
nQ7
GND
OE
V
DD
V
DD
GND
V
DD
CLK
nCL
K
Q0
nQ0
CLK
nCLK
OE
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Pin Assignment
85408I
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm package body
G Package
Top View
Block Diagram
Low Skew, 1-to-8, Differential-to-LVDS Clock
85408I
Datasheet
2©2016 Integrated Device Technology, Inc. Revision C, February 23, 2016
85408I Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1, 2 nQ6, Q6 Output Differential output pair. LVDS interface levels.
3, 4 nQ5, Q5 Output Differential output pair. LVDS interface levels.
5, 6 nQ4, Q4 Output Differential output pair. LVDS interface levels.
7, 8 nQ3, Q3 Output Differential output pair. LVDS interface levels.
9, 10 nQ2, Q2 Output Differential output pair. LVDS interface levels.
11, 12 nQ1, Q1 Output Differential output pair. LVDS interface levels.
13, 14 nQ0, Q0 Output Differential output pair. LVDS interface levels.
15 nCLK Input Pullup Inverting differential clock input.
16 CLK Input Pulldown Non-inverting differential clock input.
17, 19, 20 V
DD
Power Positive supply pins.
18, 21 GND Power Power supply ground.
22 OE Input Pullup
Output enable. Controls the enabling and disabling of outputs Qx, nQx. When HIGH,
the outputs are enabled. When LOW, the outputs are in High-Impedance. LVCMOS /
LVTTL interface levels.
23, 24 nQ7, Q7 Output Differential output pair. LVDS interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4pF
C
PD
Power Dissipation Capacitance
(per output)
4pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
3©2016 Integrated Device Technology, Inc. Revision C, February 23, 2016
85408I Datasheet
Function Tables
Table 3A. Output Enable Function Table
Table 3B. Clock Input Function Table
NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single-Ended Levels.
Inputs Outputs
OE Q[0:7], nQ[0:7]
0 High-Impedance
1 Active (default)
Inputs Outputs
Input to Output Mode PolarityCLK nCLK Q[0:7] nQ[0:7]
0 1 LOW HIGH Differential to Differential Non-Inverting
1 0 HIGH LOW Differential to Differential Non-Inverting
0 Biased; NOTE 1 LOW HIGH Single-Ended to Differential Non-Inverting
1 Biased; NOTE 1 HIGH LOW Single-Ended to Differential Non-Inverting
Biased; NOTE 1 0 HIGH LOW Single-Ended to Differential Inverting
Biased; NOTE 1 1 LOW HIGH Single-Ended to Differential Inverting
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

85408BGILF

Mfr. #:
Buy 85408BGILF
Manufacturer:
IDT
Description:
Clock Buffer Low Skew 1-to-8 Diff to LVDS Clock Dist
Lifecycle:
New from this manufacturer.
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