9©2016 Integrated Device Technology, Inc. Revision C, February 23, 2016
85408I Datasheet
Applications Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how the differential input can be wired to accept
single-ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock swing
is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V and R2/R1 =
0.609.
Figure 1. Single-Ended Signal Driving Differential Input
Recommendations for Unused Output Pins
Outputs:
LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated
with 100 across. If they are left floating, there should be no trace
attached.
V_REF
Single Ended Clock Input
V
DD
CLK
nCLK
R1
1K
C1
0.1u R2
1K
