10©2016 Integrated Device Technology, Inc. Revision C, February 23, 2016
85408I Datasheet
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the V
PP
and
V
CMR
input requirements. Figures 2A to 2F show interface
examples for the CLK/nCLK input driven by the most common
driver types. The input interfaces suggested here are examples
only. Please consult with the vendor of the driver component to
confirm the driver termination requirements. For example, in Figure
2A, the input termination applies for IDT open emitter LVHSTL
drivers. If you are using an LVHSTL driver from another vendor,
use their termination recommendation.
2A. CLK/nCLK Input Driven by an IDT
Open Emitter LVHSTL Driver
Figure 3C. CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 2E. CLK/nCLK Input
Driven by a 3.3V HCSL Driver
Figure 2B. CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 2D. CLK/nCLK Input
Driven by a 3.3V LVDS Driver
Figure 2F. CLK/nCLK Input
Driven by a 2.5V SSTL Driver
R1
50Ω
R2
50Ω
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
nCLK
3.3V
LVHSTL
IDT
LVHSTL Driver
Differential
Input
H
CSL
*R
3
*
R4
C
L
K
n
C
L
K
3
.
3V
3
.
3V
Diff
e
r
e
nti
a
l
In
p
u
t
CLK
nCLK
Differential
Input
SSTL
2.5V
Zo = 60
Ω
Zo = 60
Ω
2.5V
3.3V
R1
120
Ω
R2
120
Ω
R3
120
Ω
R4
120
Ω
11©2016 Integrated Device Technology, Inc. Revision C, February 23, 2016
85408I Datasheet
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 3. In a 100 differential
transmission line environment, LVDS drivers require a matched load
termination of 100 across near the receiver input. For a multiple
LVDS outputs buffer, if only partial outputs are used, it is
recommended to terminate the unused outputs.
Figure 3. Typical LVDS Driver Termination
3.3V
LVDS Driver
R1
100Ω
+
3.3V
50Ω
50Ω
100
Ω
Differential Transmission Line
12©2016 Integrated Device Technology, Inc. Revision C, February 23, 2016
85408I Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 85408I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 85408I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The
following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
Power (core)
MAX
= V
DD_MAX
* I
DD_MAX
= 3.465V * 90mA = 311.85mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The
maximum recommended junction temperature for devices is 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 70°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.312W * 70°C/W = 106.8°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance
JA
for 24 Lead TSSOP, Forced Convection
JA
by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 70°C/W 65.0°C/W 62°C/W

85408BGILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer Low Skew 1-to-8 Diff to LVDS Clock Dist
Lifecycle:
New from this manufacturer.
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