CY7C026A
16 K × 16 Dual-Port Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-06046 Rev. *J Revised November 18, 2015
16 K × 16 Dual-Port Static RAM
Features
■ True dual-ported memory cells that allow simultaneous access
of the same memory location
■ 16 K × 16 organization (CY7C026A)
■ 0.35 micron CMOS for optimum speed and power
■ High speed access: 15, and 20 ns
■ Low operating power
■ Active: I
CC
= 180 mA (typical)
■ Standby: I
SB3
= 0.05 mA (typical)
■ Fully asynchronous operation
■ Automatic power-down
■ Expandable data bus to 32 bits or more using Master/Slave
chip select when using more than one device
■ On-chip arbitration logic
■ Semaphores included to permit software handshaking
between ports
■ INT flags for port-to-port communication
■ Separate upper-byte and lower-byte control
■ Pin select for Master or Slave
■ Commercial and Industrial temperature ranges
■ Available in 100-pin thin quad plastic flatpack (TQFP)
■ Pb-free packages available
Functional Description
The CY7C026A is a low power CMOS 16 K × 16 dual-port static
RAM. Various arbitration schemes are included on the devices
to handle situations when multiple processors access the same
piece of data. Two ports are provided, permitting independent,
asynchronous access for reads and writes to any location in
memory. The device can be utilized as standalone 16-bit
dual-port static RAM or multiple devices can be combined to
function as a 32-bit or wider master/slave dual-port static RAM.
An M/S
pin is provided for implementing 32-bit or wider memory
applications without the need for separate master and slave
devices or additional discrete logic. Application areas include
interprocessor/multiprocessor designs, communications status
buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE
), Read
or Write Enable (R/W
), and Output Enable (OE). Two flags are
provided on each port (BUSY
and INT). BUSY signals that the
port is trying to access the same location currently being
accessed by the other port. The Interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on
each port by the chip enable pin.
The CY7C026A is available in 100-pin thin quad plastic flatpack
(TQFP) packages.
For a complete list of related documentation, click here.
CY7C026A16 K × 16 Dual-Port Static RAM
