CY7C026A
Document Number: 38-06046 Rev. *J Page 4 of 24
Pin Configurations
Figure 1. 100-pin TQFP pinout (Top View)
1
3
2
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
74
72
71
NC
NC
NC
A
6L
A
5L
A
4L
INT
L
A
2L
A
0L
GND
M/S
A
0R
A
1R
A
1L
A
3L
BUSY
R
INT
R
A
2R
A
3R
A
4R
A
5R
NC
NC
NC
BUSY
L
58
57
56
55
54
53
52
51
CY7C026A (16 K × 16)
NC
NC
NC
NC
I/O
10L
I/O
11L
I/O
15L
I/O
13L
I/O
14L
GND
I/O
0R
VCC
I/O
3R
GND
I/O
12L
I/O
1R
I/O
2R
I/O
4R
I/O
5R
I/O
6R
NC
NC
NC
NC
VCC
17
16
15
9
10
12
11
13
14
8
7
6
4
5
18
19
20
21
22
23
24
25
I/O
9L
I/O
8L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
0L
I/O
2L
I/O
1L
VCC
R/W
L
UB
L
LB
L
GND
I/O
3L
SEM
L
CE
L
A
13L
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
OE
L
34 35 36 424139 403837 43 44 45 5048 494746
A
6R
A
7R
A
8R
A
9R
A
10R
A
11R
CE
R
A
13R
UB
R
GND
R/W
R
GND
I/O
14R
LB
R
A
12R
OE
R
I/O
15R
I/O
13R
I/O
12R
I/O
11R
I/O
10R
I/O
9R
I/O
8R
I/O
7R
SEM
R
3332313029282726
CY7C026A
Document Number: 38-06046 Rev. *J Page 5 of 24
Pin Definitions
Left Port Right Port Description
CE
L
CE
R
Chip enable
R/W
L
R/W
R
Read/Write enable
OE
L
OE
R
Output enable
A
0L
–A
13L
A
0R
–A
13R
Address
I/O
0L
–I/O
15L
I/O
0R
–I/O
15R
Data bus input/output
SEM
L
SEM
R
Semaphore enable
UB
L
UB
R
Upper byte select (I/O
8
–I/O
15
for × 16 devices)
LB
L
LB
R
Lower byte select (I/O
0
–I/O
7
for × 16 devices)
INT
L
INT
R
Interrupt flag
BUSY
L
BUSY
R
Busy flag
M/S
Master or slave select
V
CC
Power
GND Ground
NC No connect
Selection Guide
Parameter
CY7C026A
-15
CY7C026A
-20
Unit
Maximum access time 15 20 ns
Typical operating current 190 180 mA
Typical standby current for I
SB1
(Both ports TTL level) 50 45 mA
Typical standby current for I
SB3
(Both ports CMOS level) 0.05 0.05 mA
CY7C026A
Document Number: 38-06046 Rev. *J Page 6 of 24
Architecture
The CY7C026A consists of an array of 16K words of 16 bits each
of dual-port RAM cells, I/O and address lines, and control signals
(CE
, OE, R/W). These control pins permit independent access
for reads or writes to any location in memory. To handle
simultaneous writes/reads to the same location, a BUSY
pin is
provided on each port. Two Interrupt (INT
) pins can be utilized
for port-to-port communication. Two Semaphore (SEM
) control
pins are used for allocating shared resources. With the M/S
pin,
the devices can function as a master (BUSY
pins are outputs) or
as a slave (BUSY
pins are inputs). The devices also have an
automatic power down feature controlled by CE
. Each port is
provided with its own Output Enable control (OE
), which allows
data to be read from the device.
Functional Overview
Write Operation
Data must be set up for a duration of t
SD
before the rising edge
of R/W
to either the R/W pin (see Figure 6 on page 15) or the CE
pin (see Figure 7 on page 15). Required inputs for
non-contention operations are summarized in Table 1.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must occur before the data is read on the output; otherwise the
data read is not deterministic. Data is valid on the port t
DDD
after
the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE and
CE
pins. Data is available t
ACE
after CE or t
DOE
after OE is
asserted. If the user wishes to access a semaphore flag, then the
SEM
pin must be asserted instead of the CE pin, and OE must
also be asserted.
Table 1. Non-Contending Read/Write
Inputs Outputs
Operation
CE R/W OE UB LB SEM I/O
8
I/O
15
I/O
0
I/O
7
H X X X X H High Z High Z Deselected: Power-down
X X X H H H High Z High Z Deselected: Power-down
L L X L H H Data in High Z Write to upper byte only
L L X H L H High Z Data in Write to lower byte only
L L X L L H Data in Data in Write to both bytes
L H L L H H Data out High Z Read upper byte only
L H L H L H High Z Data out Read lower byte only
L H L L L H Data out Data out Read both bytes
X X H X X X High Z High Z Outputs disabled
H H L X X L Data out Data out Read data in semaphore flag
H H L H H L Data out Data out Read data in semaphore flag
H X X X L Data in Data in Write D
IN0
into semaphore flag
H X H H L Data in Data in Write D
IN0
into semaphore flag
L X X L X L Not allowed
L X X X L L Not allowed

CY7C026A-20AXCT

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
SRAM 256Kb 20ns 16K x 16 Dual Port SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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