Document Number: 38-06046 Rev. *J Page 12 of 24
Switching Characteristics
Over the Operating Range
Parameter
[9]
Description
CY7C026A
Unit-15 -20
Min Max Min Max
Read Cycle
t
RC
Read cycle time 15 – 20 – ns
t
AA
Address to data valid – 15 – 20 ns
t
OHA
Output hold from address change 3 – 3 – ns
t
ACE
[10]
CE LOW to data valid – 15 – 20 ns
t
DOE
OE LOW to data valid – 10 – 12 ns
t
LZOE
[11, 12, 13]
OE LOW to Low Z 3 – 3 – ns
t
HZOE
[11, 12, 13]
OE HIGH to High Z – 10 – 12 ns
t
LZCE
[11, 12, 13]
CE LOW to Low Z 3 – 3 – ns
t
HZCE
[11, 12, 13]
CE HIGH to High Z – 10 – 12 ns
t
PU
[13]
CE LOW to Power-up 0 – 0 – ns
t
PD
[13]
CE HIGH to Power-down – 15 – 20 ns
t
ABE
[10]
Byte enable access time – 15 – 20 ns
Write Cycle
t
WC
Write cycle time 15 – 20 – ns
t
SCE
[10]
CE LOW to write end 12 – 15 – ns
t
AW
Address valid to write end 12 – 15 – ns
t
HA
Address hold From write end 0 – 0 – ns
t
SA
[10]
Address setup to write start 0 – 0 – ns
t
PWE
Write pulse width 12 – 15 – ns
t
SD
Data setup to write end 10 – 15 – ns
t
HD
[14]
Data hold from write end 0 – 0 – ns
t
HZWE
[12, 13]
R/W LOW to High Z – 10 – 12 ns
t
LZWE
[12, 13]
R/W HIGH to Low Z 3 – 3 – ns
t
WDD
[15]
Write pulse to data delay – 30 – 45 ns
t
DDD
[15]
Write data valid to read data valid – 25 – 30 ns
Notes
9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified I
OI
/I
OH
and 30 pF load capacitance.
10. To access RAM, CE
= L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire t
SCE
time.
11. At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
12. Test conditions used are Load 2.
13. This parameter is guaranteed but not tested.
14. For 15 ns industrial parts t
HD
minimum is 0.5 ns.
15. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Figure 10 on page 17.
