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8535AG-21LF

P1-P3P4-P6P7-P9P10-P12P13-P15
1©2015 Integrated Device Technology, Inc. Revision B, December 8, 2015
General Description
The 8535-21 is a low skew, high performance 1-to-2
LVCMOS/LVTTL-to-3.3V LVPECL fanout buffer. The 8535-21 has
two single-ended clock inputs. The single-ended clock input accepts
LVCMOS or LVTTL input levels and translate them to 3.3V LVPECL
levels. The clock enable is internally synchronized to eliminate runt
clock pulses on the output during asynchronous
assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make the
8535-21 ideal for those applications demanding well defined
performance and repeatability.
Features
• Two differential 3.3V LVPECL outputs
• Selectable CLK0 or CLK1 inputs for redundant and multiple
frequency fanout applications
• CLK0 or CLK1 can accept the following input levels:
LVCMOS or LVTTL
• Maximum output frequency: 266MHz
• Translates LVCMOS and LVTTL levels to 3.3V LVPECL levels
• Output skew: 20ps (maximum)
• Part-to-part skew: 300ps (maximum)
• Propagation delay: 1.6ns (maximum)
• Additive phase jitter, RMS: 0.03ps (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Available in lead-free (RoHS 6)
Block Diagram
Q0
Q0
Q1
Q1
CLK_EN
CLK_SEL
CLK1
CLK0
D
LE
Q
0
1
Pullup
Pulludown
Pulludown
Pulludown
1
2
3
4
5
6
7
V
EE
CLK_EN
CLK_SEL
CLK0
V
EE
CLK1
V
CC
14
13
12
11
10
9
8
V
CC
Q0
Q0
nc
Q1
Q1
V
CC
Pin Assignment
8535-21
14 Lead TSSOP
4.40mm x 5.0mm x 0.925mm package body
G Package
Top View
8535-21
Datasheet
Low Skew, 1-to-2 LVCMOS/ LVTTL-to-3.3V
LVPECL CLock Generator
2©2015 Integrated Device Technology, Inc. Revision B, December 8, 2015
8535-21 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1, 5 V
EE
Power Negative supply pins.
2 CLK_EN Input Pullup
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
When LOW, Qx outputs are forced low, Qx
outputs are forced high.
LVCMOS/LVTTL interface levels.
3 CLK_SEL Input Pulldown
Clock select input. When HIGH, selects CLK1 input.
When LOW, selects CLK0 input. LVCMOS/LVTTL interface levels.
4, 6 CLK0, CLK1 Input Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels.
7, 8, 14 V
CC
Power Power supply pins.
9, 10 Q1
, Q1 Output Differential output pair. LVPECL interface levels.
11 nc Unused No connect.
12, 13 Q0
, Q0 Output Differential output pair. LVPECL interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
3©2015 Integrated Device Technology, Inc. Revision B, December 8, 2015
8535-21 Datasheet
Function Tables
Table 3A. Control Input Function Table
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0 and CLK1 inputs as described in Table 3B.
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs Outputs
CLK_EN CLK_SEL Selected Source Q0, Q1 Q0
, Q1
0 0 CLK0 Disabled; Low Disabled; High
0 1 CLK1 Disabled; Low Disabled; High
1 0 CLK0 Enabled Enabled
1 1 CLK1 Enabled Enabled
Inputs Outputs
CLK0 or CLK1 Q0, Q1 Q0
, Q1
0LOWHIGH
1HIGHLOW
Enabled
Disabled
CLK0, CLK1
CLK_EN
Q0, Q1
nQ0, nQ1
CLK0, CLK1
CLK_EN
Q0, Q1
Q0, Q1
P1-P3P4-P6P7-P9P10-P12P13-P15

8535AG-21LF

Mfr. #:
Buy 8535AG-21LF
Manufacturer:
IDT
Description:
Clock Buffer 1:4 LVCMOS-to-3.3V LVPECL Fanout Buffer
Lifecycle:
New from this manufacturer.
Delivery:
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