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8535AG-21LF

P1-P3P4-P6P7-P9P10-P12P13-P15
4©2015 Integrated Device Technology, Inc. Revision B, December 8, 2015
8535-21 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
CC
= 3.3V ± 5%, T
A
= 0°C to 70°C
Table 4B. LVCMOS/LVTTL DC Characteristics, V
CC
= 3.3V ± 5%, T
A
= 0°C to 70°C
Table 4C. LVPECL DC Characteristics, V
CC
= 5%, T
A
= 0°C to 70°C
NOTE 1: Outputs termination with 50 to V
CC
– 2V.
Item Rating
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance,
JA
93.2C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
CC
Positive Supply Voltage 3.135 3.3 3.465 V
I
EE
Power Supply Current 50 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage 2 V
CC
+ 0.3 V
V
IL
Input Low Voltage
CLK0, CLK1 -0.3 1.3 V
CLK_EN,
CLK_SEL
-0.3 0.8 V
I
IH
Input High Current
CLK0, CLK1,
CLK_SEL
V
CC
= V
IN
= 3.465 150 µA
CLK_EN V
CC
= V
IN
= 3.465 5 µA
I
IL
Input Low Current
CLK0, CLK1,
CLK_SEL
V
CC
= 465V, V
IN
= 0V -5 µA
CLK_EN V
CC
= 465V, V
IN
= 0V -150 µA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OH
Output High Current; NOTE 1 V
CC
– 1.4 V
CC
– 0.9 µA
V
OL
Output Low Current; NOTE 1 V
CC
– 2.0 V
CC
– 1.7 µA
V
SWING
Peak-to-Peak Output Voltage Swing 0.6 1.0 V
5©2015 Integrated Device Technology, Inc. Revision B, December 8, 2015
8535-21 Datasheet
AC Electrical Characteristics
Table 5. AC Characteristics, V
CC
= 3.3V ± 5%, T
A
= 0°C to 70°C
NOTE: All parameters measured at ƒ 266MHz unless noted otherwise.
NOTE 1: Measured from V
CC
/2 of the input to the differential output crossing point. The part does not add jitter.
NOTE 2: Driving only one input clock.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
CC
/2 of the input to the differential output crossing point.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential cross points.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 266 MHz
t
PD
Propagation Delay; NOTE 1 ƒ 266MHz 1.0 1.6 ns
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section; NOTE 2
156.25MHz, Integration Range:
12kHz – 20MHz
0.03 ps
tsk(o) Output Skew; NOTE 3, 4 20 ps
tsk(pp) Part-to-Part Skew; NOTE 4, 5 300 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% @ 50MHz 300 600 ps
odc Output Duty Cycle ƒ 200MHz 45 55 %
6©2015 Integrated Device Technology, Inc. Revision B, December 8, 2015
8535-21 Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements have
issues. The primary issue relates to the limitations of the equipment.
Often the noise floor of the equipment is higher than the noise floor
of the device. This is illustrated above. The device meets the noise
floor of what is shown, but can actually be lower. The phase noise is
dependant on the input source and measurement equipment.
SSB Phase Noise dBc/Hz
Offset Frequency (Hz)
1k 10k 100k 1M 10M 100M
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
P1-P3P4-P6P7-P9P10-P12P13-P15

8535AG-21LF

Mfr. #:
Buy 8535AG-21LF
Manufacturer:
IDT
Description:
Clock Buffer 1:4 LVCMOS-to-3.3V LVPECL Fanout Buffer
Lifecycle:
New from this manufacturer.
Delivery:
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