10©2015 Integrated Device Technology, Inc. Revision B, December 8, 2015
8535-21 Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 8535-21.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 8535-21 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 50mA = 173.25mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_
MAX
(3.3V, with all outputs switching) = 173.25mW + 60mW = 233.25mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and it directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a moderate air
flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 85.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.233W * 85.5°C/W = 90°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (single layer or multi-layer).
Table 6. Thermal Resitance
JA
for 48 Lead TQFP, Forced Convection
JA
vs. Air Flow
Linear Feet per Minute 0200500
Single-Layer PCB, JEDEC Standard Test Boards 146.4°C/W 125.2°C/W 112.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 93.2°C/W 85.5°C/W 81.2°C/W
11©2015 Integrated Device Technology, Inc. Revision B, December 8, 2015
8535-21 Datasheet
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 4.
Figure 4. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
V
CC
– 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
– 0.9V
(V
CC_MAX
– V
OH_MAX
) = 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.7V
(V
CC_MAX
– V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX –
(V
CC_MAX
– 2V))/R
L
] * (V
CC_MAX
– V
OH_MAX
) = [(2V - (V
CC_MAX
– V
OH_MAX
))/R
L
] * (V
CC_MAX
– V
OH_MAX
) =
[(2V – 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX –
(V
CC_MAX
– 2V))/R
L
] * (V
CC_MAX
– V
OL_MAX
) = [(2V – (V
CC_MAX
– V
OL_MAX
))/R
L
] * (V
CC_MAX
– V
OL_MAX
) =
[(2V – 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
V
OUT
V
CC
V
CC
- 2V
Q1
RL
50Ω
12©2015 Integrated Device Technology, Inc. Revision B, December 8, 2015
8535-21 Datasheet
Reliability Information
Table 7.
JA
vs. Air Flow Table for a 14 Lead TSSOP
Transistor Count
The transistor count for 8535-21 is: 412
Package Outline and Package Dimension
Package Outline - G Suffix for 14 Lead TSSOP Table 8. Package Dimensions
Reference Document: JEDEC Publication 95, MO-153
JA
vs. Air Flow
Linear Feet per Minute 0200500
Single-Layer PCB, JEDEC Standard Test Boards 146.4°C/W 125.2°C/W 112.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 93.2°C/W 85.5°C/W 81.2°C/W
All Dimensions in Millimeters
Symbol Minimum Maximum
N 14
A 1.20
A1 0.5 0.15
A2 0.80 1.05
b 0.19 0.30
c 0.09 0.20
D 4.90 5.10
E 6.40 Basic
E1 4.30 4.50
e 0.65 Basic
L 0.45 0.75
aaa 0.10

8535AG-21LF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 1:4 LVCMOS-to-3.3V LVPECL Fanout Buffer
Lifecycle:
New from this manufacturer.
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