PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 8 — 8 November 2017 10 of 34
NXP Semiconductors
PCA9538
8-bit I
2
C-bus and SMBus low power I/O port with interrupt and reset
6.7 Bus transactions
Data is transmitted to the PCA9538 registers using the write mode as shown in Figure 7
and Figure 8
. Data is read from the PCA9538 registers using the read mode as shown in
Figure 9
and Figure 10. These devices do not implement an auto-increment function so
once a command byte has been sent, the register which was addressed will continue to
be accessed by reads until a new command byte has been sent.
Expanded diagram is shown in Figure 18.
Fig 7. Write to output port register
0 AS
slave address
START condition R/W acknowledge
from slave
002aae708
00000010
command byte
A
acknowledge
from slave
12345678SCL 9
SDA
DATA 1 A
write to port
data out from port
t
v(Q)
acknowledge
from slave
DATA 1 VALID
data to port
1100A1A01
P
STOP
condition
Fig 8. Write to configuration or polarity inversion registers
0 AS
slave address
START condition R/W acknowledge
from slave
002aae709
0000011/00
command byte
A
acknowledge
from slave
12345678SCL 9
SDA
DATA 1 A
data to register
acknowledge
from slave
data to register
1100A1A01
P
STOP
condition
